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参数资料
| 型号： | LTC1164ACSW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC FILTER BUILDING BLOCK 24-SOIC |
| 标准包装： | 32 |
| 滤波器类型： | 通用开关电容器 |
| 频率 - 截止或中心： | 20kHz |
| 滤波器数： | 4 |
| 滤波器阶数： | 8th |
| 电源电压： | ±2.37 V ~ 8 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC |
| 包装： | 管件 |
LTC1164
7
1164fa
Power Supplies (Pins 7,19)
They should be bypassed with 0.1F ceramic disc. Low
noise, non-switching, power supplies are recommended.
The device operates with a single 5V supply and with dual
supplies. The absolute maximum operating power supply
voltage is ±8.25V. Supply reversal is not allowed and can
cause latch up. When using dual supplies, loads between
the positive and negative supply (even light loads) can
cause momentary supply reversal during power-up. A
clamp diode from each supply to ground will prevent
reversal and latch problems.
Clock (Pin 18)
For ±5V supplies the logic threshold level is 1.8V. For ±8V
and 0 to 5V supplies the logic threshold level is 2.8V. The
logic threshold levels vary ±100mV over the full military
temperature range. The recommended duty cycle of the
input clock is 50%, although for clock frequencies below
500kHz the clock “on” time can be as low as 200ns. The
maximum clock frequency for single 5V supply and Q
values <5 is 500kHz and for ±5V supplies and above is
1MHz. The clock input can be applied before power is
turned on as long as there is no chance the clock signal will
go below the V– supply.
AGND (PIN 6)
When the LTC1164 operates with dual supplies, Pin 6
should be tied to system ground. When the LTC1164
operates with a single positive supply, the analog ground
pin should be tied to 1/2 supply and it should be bypassed
with a 4.7F solid tantalum in parallel with a 0.1F ceramic
disc, Figure 2. The positive input of all the internal op
amps, as well as the common reference of all the internal
switches, are internally tied to the analog ground pin.
Because of this, a very “clean” ground is recommended.
50/100 (Pin 17)
By tying Pin 17 to V+, all filter sections operate with a clock-
to-center frequency ratio internally set at 50:1. When Pin
17 is at mid-supplies, sections B and C operate with (fCLK/
fO) = 50:1 and sections A and D operate at (100:1). When
Pin 17 is shorted to the negative supply pin, all filter
sections operate with (fCLK/fO) = 100:1.
Figure 2. Single Supply Operation
LTC1164 PD01
TO DIGITAL
GROUND
ANALOG
GROUND
PLANE
NOTE: PIN 5, 8, 20, IF NOT USED, SHOULD BE CONNECTED TO PIN 6.
*LT1004 CAN BE REPLACED WITH A 7.5k RESISTOR FOR V+ >6.5V
7.5k
LT1004*
V+
124
223
322
421
520
V+/2
619
4.7F
0.1F
718
817
916
10
15
11
14
12
13
CLOCK INPUT
V+ = 15V, TRIP VOLTAGE = 7V
V+ = 10V, TRIP VOLTAGE = 6.4V
V+ = 5V, TRIP VOLTAGE = 3V
LTC1164
AGND
V+
V –
CLK
50/100
+
UU
U
PI FU CTIO S
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相关代理商/技术参数 |
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|---|---|
| LTC1164AM | 制造商:LINER 制造商全称:Linear Technology 功能描述:Low Power, Low Noise, Quad Universal Filter Building Block |
| LTC1164AMJ | 制造商:Linear Technology 功能描述:Active Filter Quad SW-CAP UNIV 8th Order 20kHz 24-Pin CDIP |
| LTC1164C | 制造商:LINER 制造商全称:Linear Technology 功能描述:Low Power, Low Noise, Quad Universal Filter Building Block |
| LTC1164CJ | 制造商:Linear Technology 功能描述:Active Filter Quad SW-CAP UNIV 8th Order 20kHz 24-Pin CDIP |
| LTC1164CN | 功能描述:IC FILTER BUILDING BLOCK 24-DIP RoHS:否 类别:集成电路 (IC) >> 接口 - 滤波器 - 有源 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 滤波器类型:连续时间，带通低通 频率 - 截止或中心:150kHz 滤波器数:4 滤波器阶数:8th 电源电压:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) |
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