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参数资料
| 型号： | LTC1278-5ISW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | IC A/DCONV SAMPLNG W/SHTDN24SOIC |
| 标准包装： | 32 |
| 位数： | 12 |
| 采样率（每秒）： | 500k |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 150mW |
| 电压电源： | 双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极；1 个单端，双极 |
12
LTC1278
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 9a. Full-Scale Adjust Circuit
LTC1278
AIN
AGND
LTC1278 F9a
R4
100
FULL-SCALE
ADJUST
R3
10k
R2
10k
R1
50
V1
–
+
A1
ADDITIONAL PINS OMITTED FOR CLARITY
±20LSB TRIM RANGE
Unipolar Offset and Full-scale Error Adjustments
In applications where absolute accuracy is important, then
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 9a
shows the extra components required for full-scale error
adjustment. If both offset and full-scale adjustments are
needed, the circuit in Figure 9b can be used. For zero offset
error apply 0.61mV (i.e., 1/2LSB) at the input and adjust
the offset trim until the LTC1278 output code flickers
between 0000 0000 0000 and 0000 0000 0001. For zero
full-scale error apply an analog input of 4.99817V (i.e., FS
– 1 1/2LSB or last code transition) at the input and adjust
R5 until the LTC1278 output code flickers between 1111
1111 1110 and 1111 1111 1111.
Bipolar Offset and Full-scale Error Adjustments
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset must be
adjusted before full-scale error. Bipolar offset error ad-
justment is achieved by trimming the offset of the op amp
driving the analog input of the LTC1278 while the input
voltage is 1/2LSB below ground. This is done by applying
an input voltage of – 0.61mV (– 0.5LSB) to the input in
Figure 9c and adjusting the R8 until the ADC output code
flickers between 0000 0000 0000 and 1111 1111 1111.
For full-scale adjustment, an input voltage of 2.49817V
(FS – 1.5LSBs) is applied to the input and R5 is adjusted
until the output code flickers between 0111 1111 1110
and 0111 1111 1111.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1278, a printed circuit board is
required. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the AVDD and VREF pins as shown in
Figure 10. For the bipolar mode, a 0.1
F ceramic provides
adequate bypassing for the VSS pin. The capacitors must
be located as close to the pins as possible. The traces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Input signal leads to AIN and signal return leads from
AGND (Pin 3) should be kept as short as possible to
minimize input noise coupling. In applications where this
is not possible, a shielded cable between source and ADC
is recommended.
Figure 9c. LTC1278 Bipolar Offset and Full-Scale Adjust Circuit
Figure 9b. LTC1278 Unipolar Offset and Full-Scale Adjust Circuit
AIN
LTC1278 F9b
R2
10k
R4
100k
R1
10k
5V
R9
20
ANALOG
INPUT
0V TO 5V
R3
100k
5V
R8
10k
OFFSET
ADJUST
R6
400
R5
4.3k
FULL-SCALE
ADJUST
R7
100k
–
+
LTC1278
AIN
LTC1278 F9c
R2
10k
R4
100k
R1
10k
ANALOG
INPUT
R3
100k
5V
R8
20k
OFFSET
ADJUST
R6
200
R5
4.3k
FULL-SCALE
ADJUST
R7
100k
–
+
LTC1278
–5V
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