参数资料
型号: LTC1325CN#PBF
厂商: Linear Technology
文件页数: 23/24页
文件大小: 0K
描述: IC BATTERY MANAGMNT SYSTEM 18DIP
标准包装: 20
功能: 充电管理
电池化学: 铅酸,锂离子,镍镉,镍氢
电源电压: 4.5 V ~ 16 V
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 18-DIP(0.300",7.62mm)
供应商设备封装: 18-DIP
包装: 管件
LTC1325
APPLICATIO N S I N FOR M ATIO N
LABEL MNEMONIC OPERAND
COMMENTS
LABEL MNEMONIC OPERAND
COMMENTS
LDAA
STAA
LDAA
STAA
LDX
#$51
$1028
#$39
$1009
#$1000
Write control byte to the SPCR
Setup Port D DDRD
Port D Bit 0 is CS
Load port base ADDR
LOOP4 TST
BPL
LDAA
ANDA
STAA
$1029
LOOP4
$102A
#$03
HIDATA
Check for SPI transfer
complete bit
Get A/D high byte
Mask off unwanted bits
Store in user memory
CSLOW
LOOP1
LOOP2
LOOP3
BCLR
LDAA
STAA
TST
BPL
LDAA
STAA
TST
BPL
LDAA
STAA
TST
BPL
LDAA
$08,X,#$01
#$02
$102A
$1029
LOOP1
#$24
$102A
$1029
LOOP2
#$03
$102A
$1029
LOOP3
#$C0
Take CS low
Send Byte #1 (MSB) with
START bit
Check for SPI transfer
complete bit
Send Byte 2
Check for SPI transfer
complete bit
Send Byte 3
Check for SPI transfer
complete bit
Send Byte 4
LDAA
STAA
LOOP5 TST
BPL
LDAA
STAA
LDAA
STAA
LOOP6 TST
BPL
LDAA
STAA
BSET
BRA
#$00
$102A
$1029
LOOP5
$102A
LODATA
#$00
$102A
$1029
LOOP6
$102A
STATUS
$08,X,#$01
CSLOW
Send dummy Byte #1
Check for SPI transfer
complete bit
Get A/D low byte
Store in user memory
Send dummy Byte #2
Check for SPI transfer
complete bit
Get STATUS byte
Store in user memory
Raise CS high
Loop for continuous readings
STAA
$102A
TYPICAL APPLICATIO N
Wide Voltage Battery Charger
V DC
25V
MBR320
NOTE 1
NOTE 1
NOTE 7
NOTE 2
R11
220 ?
NOTE 3
D3
R12
C1
1 μ F
+
1/2W
D4
1N4744A
15V
1N4740A
C2
0.1 μ F
100k
P1
IRF9Z30
D1
1N5818
R TRK
MPU
(e.g. 8051)
REG
V DD
L1
62 μ H
p1.4
D OUT
D IN
PGATE
DIS
R13
R6
R DIS
p1.3
p1.2
C REG
4.7 μ F
+
R1
R2
R3
CS V BAT
CLK T BAT
LTF T AMB
MCV V IN
HTF SENSE
GND FILTER
LTC1325
NOTE 6
C5
0.1 μ F
THERM 2
R5
THERM 1
R7
R14
100 ?
+ C4
22 μ F
V BAT
NOTE 5
R9
R10
N1
IRF830
NOTE 1
NOTE 4
D2
1N4744A
R4
C F
1 μ F
C3
500pF
R8
100 ?
R SENSE
15V
NOTE 1: NEEDED WHEN V DC > 16V OR MAXIMUM
BATTERY VOLTAGE, V BAT > 16V.
NOTE 2: REGULATOR. OMIT THIS BLOCK AND SHORT
VDD TO V DC WHEN V DC < 16V.
NOTE 3: LEVEL SHIFTER. OMIT THIS BLOCK AND SHORT
PGATE TO P1 GATE WHEN V DC < 16V.
NOTE 4: ZENER TO CLAMP V BAT TO BELOW V DD .
OMIT WHEN V DC < 16V.
NOTE 5: EXTERNAL BATTERY DIVIDER. NEEDED WHEN
MAXIMUM BATTERY VOLTAGE, V BAT > 16V.
NOTE 6: V IN IS AN UNCOMMITTED A/D CHANNEL.
NOTE 7: OPTIONAL DIODE TO PREVENT BATTERY
DRAIN WHEN THE CHARGING SUPPLY IS POWERED
DOWN (SEE SECTION 2, HARDWARE DESIGN
PROCEDURE).
1325 TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
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