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参数资料
| 型号： | LTC1403IMSE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 2.8MSPS 10-MSOP |
| 标准包装： | 50 |
| 位数： | 12 |
| 采样率（每秒）： | 2.8M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 12mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
| 包装： | 管件 |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
| 产品目录页面： | 1346 (CN2011-ZH PDF) |
| 配用： | DC1082A-D-ND - BOARD SAR ADC LTC1403A DC1082A-C-ND - BOARD SAR ADC LTC1403A-1 |
LTC1403/LTC1403A
14
1403fb
APPLICATIONS INFORMATION
Figure 6. DSP Serial Interface to TMS320C54x
rst and then buffer this signal with the appropriate number
of inverters to drive the serial clock input of the processor
serial port. Use the falling edge of the clock to latch data
from the Serial Data Output (SDO) into your processor
serial port. The 14-bit Serial Data will be received right
justied, in a 16-bit word with 16 or more clocks per frame
sync. It is good practice to drive the LTC1403/LTC1403A
SCK input rst to avoid digital noise interference during
the internal bit comparison decision by the internal high
speed comparator. Unlike the CONV input, the SCK input
is not sensitive to jitter because the input signal is already
sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out 12/14 bits in the output data stream beginning at the
third rising edge of SCK after the rising edge of CONV.
SDO is always in high impedance mode when it is not
sending out data bits. Please note the delay specication
from SCK to a valid SDO. SDO is always guaranteed to
be valid by the next rising edge of SCK. The 16-bit output
data stream is compatible with the 16-bit or 32-bit serial
port of most processors.
HARDWARE INTERFACE TO TMS320C54X
The LTC1403/LTC1403A is a serial output ADC whose
interface has been designed for high speed buffered
serial ports in fast digital signal processors (DSPs).
Figure 6 shows an example of this interface using a
TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments,
in real time, at the full 2.8Msps conversion rate of the
LTC1403/LTC1403A. The DSP assembly code sets frame
sync mode at the BFSR pin to accept an external posi-
tive going pulse and the serial clock at the BCLKR pin to
accept an external positive edge clock. Buffers near the
LTC1403/LTC1403A may be added to drive long tracks to
the DSP to prevent corruption of the signal to LTC1403/
LTC1403A. This conguration is adequate to traverse a
typical system board, but source resistors at the buffer
outputs and termination resistors at the DSP, may be
needed to match the characteristic impedance of very
long transmission lines. If you need to terminate the SDO
transmission line, buffer it rst with one or two 74ACTxx
gates. The TTL threshold inputs of the DSP port respond
properly to the 3V swing from the SDO pin.
1403A F09
7
10
9
8
6
3-WIRE SERIAL
INTERFACELINK
VDD
CONV
SCK
LTC1403/
LTC1403A
SDO
VCC
BFSR
BCLKR
TMS320C54x
BDR
GND
CONV
0V TO 3V LOGIC SWING
CLK
3V
5V
B13
B12
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