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| 型号： | LTC1434IGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK 3.3V/5V/ADJ 20SSOP |
| 标准包装： | 55 |
| 类型： | 降压（降压） |
| 输出类型： | 两者兼有 |
| 输出数： | 1 |
| 输出电压： | 3.3V，5V，可调 |
| 输入电压： | 3 V ~ 13.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 最高 700kHz |
| 电流 - 输出： | 450mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 20-SSOP |
LTC1433/LTC1434
OPERATIO N
(Refer to Functional Diagram)
Having only the small MOSFET on with low load current
reduces switching and gate charge losses, hence boosting
efficiency. For the device to go into low current mode, two
conditions must be satisfied: the peak current of the
inductor should not exceed 260mA and the voltage at the
I TH pin should not exceed 0.6V. When either one of the
conditions is exceeded, the big MOSFET will be turned on
at the next clock cycle.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the rate of change of inductor current
during the on cycle decreases. This reduction means that
the P-channel MOSFETs will remain on for more than one
oscillator cycle since the I COMP is not tripped. Further
reduction in input supply voltage will eventually cause the
P-channel MOSFET to be turned on 100%, i.e., DC. The
output voltage will then be determined by the input voltage
minus the voltage drop across the MOSFETs. Typically
under dropout, both the power MOSFETs are on since the
voltage on the I TH pin is greater than 0.6V.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC1434 to
allow the oscillator to be synchronized to an external
APPLICATIO N S I N FOR M ATIO N
The basic LTC1434 application circuit is shown in
Figure 1. External component selection is driven by the
load requirement and begins with the selection of C OSC
source connected to the PLLIN pin. The output of the
phase detector at the PLL LPF pin is also the control input
of the oscillator, which operates over a 0V to 2.4V range
corresponding to – 30% to + 30% in the oscillator’s center
frequency. When locked, the PLL aligns the turn-on of the
MOSFETs to the rising edge of the synchronizing signal.
When the PLLIN is left open, PLL LPF goes low, forcing the
oscillator to minimum frequency.
Power-On Reset
The POR pin is an open-drain output which pulls low when
the regulator is out of regulation. When the output voltage
rises to within 5% of regulation, a timer is started which
releases POR after 2 16 (65536) oscillator cycles. In shut-
down the POR output is pulled low.
Short-Circuit Protection
When the output is shorted to ground, the frequency of the
oscillator will be reduced to about 1/4.5 of its designed
rate. This low frequency allows the inductor current to
discharge, thereby preventing runaway. The oscillator’s
frequency will gradually increase to its designed rate when
the output voltage increases above 0.65V.
The value of C OSC is calculated from the desired operating
frequency. Assume the phase-locked loop has no external
oscillator input, i.e. V PLL LPF = 0V.
1 . 37 10 4 ?
( )
C OSC pF = ?
? Frequency ( kHz )
and L. Next, the Schottky diode D1 is selected followed by
C IN and C OUT .
C OSC Selection for Operating Frequency
The LTC1433/LTC1434 use a constant frequency archi-
? ?
? ? ?
?
?
?
? – 11
?
?
tecture with the frequency determined by an external
oscillator capacitor C OSC . During the on-time, C OSC is
charged by a fixed current plus an additional current
which is proportional to the output voltage of the phase
detector (V PLL LPF on LTC1434). When the voltage on the
C OSC capacitor reaches 1.19V, it is reset to ground. The
process then repeats.
A graph for selecting C OSC vs Frequency is given in Figure
2. For the LTC1433, the expression above is also appli-
cable since its oscillator is internally set up to run at a
condition equal to V PLL LPF = 0V. Therefore when using the
graph for determining the capacitance value for the oscil-
lator frequency, the V PLL LPF = 0V curve should be used for
LTC1433.
7
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