参数资料
型号: LTC1436ACGN-PLL#TRPBF
厂商: Linear Technology
文件页数: 23/28页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 24-SSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 138kHz
占空比: 99%
电源电压: 3.5 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
LTC1436A
LTC1436A-PLL/LTC1437A
APPLICATIO N S I N FOR M ATIO N
[ ]
( ) 3 1 + ( ) ( ) ( )
P MAIN =
0 . 005 50 ° C ? 25 ° C
0 . 042 ?
+ 2 . 5 ( 22 V ) ( 3 A )( 100 pF )( 250 kHz ) = 88 mW
( )
P SYNC SC ( AVG ) ? 1 + δ R DS ( ON )
= ? I
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in: R DS(ON) = 0.042 ? , C RSS = 100pF. At maximum input
voltage with T (estimated) = 50 ° C:
1 .6V 2
22 V
1 . 85
The most stringent requirement for the synchronous
N-channel MOSFET occurs when V OUT = 0 (i.e. short
circuit). In this case the worst-case dissipation rises to:
2
?? ??
With the 0.033 ? sense resistor I SC(AVG) = 4A will result,
increasing the Si4412DY dissipation to 950mW at a die
temperature of 105 ° C.
C IN is chosen for an RMS current rating of at least 1.5A at
temperature. C OUT is chosen with an ESR of 0.03 ? for low
output ripple. The output ripple in continuous mode will be
highest at the maximum input voltage. The output voltage
ripple due to ESR is approximately:
V ORIPPLE = R ESR ( ? I L ) = 0 . 03 ? ( 1 . 3 A ) = 39 mV P- P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1436A/LTC1437A. These items are also illustrated
graphically in the layout diagram of Figure 15. Check the
following in your layout:
1. Are the signal and power grounds segregated? The
LTC1436A/LTC1437A signal ground pin must return to
source of the bottom N-channel MOSFET, anode of the
Schottky diode, and (–) plate of C IN , which should have
as short lead lengths as possible.
2. Does the LTC1436A/LTC1437A V OSENSE pin connect to
the (+) plate of C OUT ? In adjustable applications, the
resistive divider R1/R2 must be connected between the
(+) plate of C OUT and signal ground. The 100pF capaci-
tor should be as close as possible to the LTC1436A/
LTC1437A.
3. Are the SENSE – and SENSE + leads routed together with
minimum PC trace spacing? The filter capacitor be-
tween SENSE + and SENSE – should be as close as
possible to the LTC1436A/LTC1437A.
4. Does the (+) plate of C IN connect to the drain of the
topside MOSFET(s) as closely as possible? This capaci-
tor provides the AC current to the MOSFET(s).
5. Is the INTV CC decoupling capacitor connected closely
between INTV CC and the power ground pin? This ca-
pacitor carries the MOSFET driver peak currents.
6. Keep the switching node SW away from sensitive small-
signal nodes. Ideally, the switch node should be placed
at the furthest point from the LTC1436A/LTC1437A.
7. Route the PLLIN line away from Boost and SW pins to
avoid unwanted pickup (Boost and SW pins have high
dV/dTs).
8. SGND should be used exclusively for grounding exter-
nal components on PLL LPF, C OSC , I TH , LBI, SFB,
V OSENSE and AUXFB pins.
9. If operating close to the minimum on-time limit, is the
sense resistor oriented on the radial axis of the induc-
tor? See Figure 13.
the (–) plate of C OUT . The power ground connects to the
14367afb
23
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