参数资料
型号: LTC1530CS8#TR
厂商: Linear Technology
文件页数: 3/24页
文件大小: 0K
描述: IC SW REG CTRLR SYNC HIPWR 8SOIC
标准包装: 2,500
应用: 控制器,Intel Pentium? II,AMD-K6?-2
输入电压: 3.75 V ~ 13.2 V
输出数: 1
输出电压: 1.3 V ~ 3.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
LTC1530
ELECTRICAL CHARACTERISTICS The q denotes specifications that apply over the full operating temperature
range, otherwise specifications are at T A = 25 ° C. PV CC = 12V unless otherwise noted. (Note 3)
SYMBOL
V OUT
? V OUT
PARAMETER
Output Voltage
Output Load Regulation
CONDITIONS
LTC1530IS8-1.9 (Note 4)
LTC1530IS8-2.5 (Note 4)
LTC1530IS8-2.8 (Note 4)
LTC1530IS8-3.3 (Note 4)
I OUT = 0 to 14A
q
q
q
q
MIN
1.881
1.862
2.475
2.450
2.772
2.744
3.267
3.234
TYP
1.9
1.9
2.5
2.5
2.8
2.8
3.3
3.3
–5
MAX
1.919
1.938
2.525
2.550
2.828
2.856
3.333
3.366
UNITS
V
V
V
V
V
V
V
V
mV
Output Line Regulation
V IN = 4.75V to 5.25V, I OUT = 0
± 1
mV
I PVCC
Operating Supply Current
Figure 3, V FB = 0V (Note 8)
15
mA
Quiescent Current
Shutdown Supply Current
Figure 3, COMP = 0.5V, V FB = 5V
Figure 3, COMP = 0 (Note 9)
q
q
1.0
45
1.4
80
mA
μ A
f OSC
Internal Oscillator Frequency
Figure 4
q
250
300
350
kHz
Oscillator Valley Voltage
Oscillator Peak Voltage
V COMP at 0% Duty Cycle
V COMP at Max Duty Cycle
2.5
3.5
V
V
G ERR
Error Amplifier Open-Loop DC Gain
(Note 5)
q
40
54
dB
g mERR
I MAX
Error Amplifier Transconductance
I MAX Sink Current
(Note 5)
V IMAX = 5V
V IMAX = 5V
q
q
1.6
170
120
2
200
200
2.8
230
300
millimho
μ A
μ A
I MAX Sink Current Tempco
V IMAX = 5V
3300
ppm/ ° C
V SHDN
SR SS
Shutdown Threshold Voltage
Internal Soft-Start Slew Rate
Figure 4, Measured at COMP Pin (Note 9)
Figure 4, COMP Pulls High, V FB = 0V
q
100
180
0.4
mV
V/ms
(Notes 9, 10)
t SS
Internal Soft-Start Wake-Up Time
Figure 4, COMP Pulls High to G1 ↑ (Note 10)
3.5
ms
t r , t f
Driver Rise and Fall Time
Figure 4
q
90
140
ns
t NOL
DC MAX
Driver Nonoverlap Time
Maximum G1 Duty Cycle
Figure 4
Figure 4
q
q
30
81
100
86
ns
%
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: If I FB is taken below GND, it is clamped by an internal diode. This
pin handles input currents ≤ 100mA below GND without latch-up. In the
positive direction, it is not clamped to PV CC .
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: The LTC1530 is tested in an op amp feedback loop which
regulates V SENSE or V OUT based on V COMP = 2V for the error amplifier.
Note 5: The Open-loop DC gain and transconductance from the V FB pin to
Note 6: The total voltage from the PV CC pin to the GND pin must be ≥ 8V
for the current limit protection circuit to be active.
Note 7: G1 and G2 begin to switch once PV CC is ≥ the undervoltage
lockout threshold voltage.
Note 8: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This current varies
with the LTC1530 operating frequency, supply voltage and the external
FETs used.
Note 9: The LTC1530 enters shutdown if COMP is pulled low.
Note 10: Slew rate is measured at the COMP pin on the transition from
shutdown to active mode.
the COMP pin are G ERR and g mERR respectively. For fixed output voltage
versions, the actual open-loop DC gain and transconductance are G ERR
and g mERR multiplied by the ratio 1.235/V OUT .
1530fa
3
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