参数资料
型号: LTC1530IS8-2.5#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO8
封装: 0.150 INCH, PLASTIC, SO-8
文件页数: 18/24页
文件大小: 301K
代理商: LTC1530IS8-2.5#PBF
3
LTC1530
1530fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOUT
Output Voltage
LTC1530IS8-1.9 (Note 4)
1.881
1.9
1.919
V
q
1.862
1.9
1.938
V
LTC1530IS8-2.5 (Note 4)
2.475
2.5
2.525
V
q
2.450
2.5
2.550
V
LTC1530IS8-2.8 (Note 4)
2.772
2.8
2.828
V
q
2.744
2.8
2.856
V
LTC1530IS8-3.3 (Note 4)
3.267
3.3
3.333
V
q
3.234
3.3
3.366
V
VOUT
Output Load Regulation
IOUT = 0 to 14A
– 5
mV
Output Line Regulation
VIN = 4.75V to 5.25V, IOUT = 0
±1mV
IPVCC
Operating Supply Current
Figure 3, VFB = 0V (Note 8)
15
mA
Quiescent Current
Figure 3, COMP = 0.5V, VFB = 5V
q
1.0
1.4
mA
Shutdown Supply Current
Figure 3, COMP = 0 (Note 9)
q
45
80
A
fOSC
Internal Oscillator Frequency
Figure 4
q
250
300
350
kHz
Oscillator Valley Voltage
VCOMP at 0% Duty Cycle
2.5
V
Oscillator Peak Voltage
VCOMP at Max Duty Cycle
3.5
V
GERR
Error Amplifier Open-Loop DC Gain
(Note 5)
q
40
54
dB
gmERR
Error Amplifier Transconductance
(Note 5)
q
1.6
2
2.8
millimho
IMAX
IMAX Sink Current
VIMAX = 5V
170
200
230
A
VIMAX = 5V
q
120
200
300
A
IMAX Sink Current Tempco
VIMAX = 5V
3300
ppm/
°C
VSHDN
Shutdown Threshold Voltage
Figure 4, Measured at COMP Pin (Note 9)
q
100
180
mV
SRSS
Internal Soft-Start Slew Rate
Figure 4, COMP Pulls High, VFB = 0V
0.4
V/ms
(Notes 9, 10)
tSS
Internal Soft-Start Wake-Up Time
Figure 4, COMP Pulls High to G1
↑ (Note 10)
3.5
ms
tr, tf
Driver Rise and Fall Time
Figure 4
q
90
140
ns
tNOL
Driver Nonoverlap Time
Figure 4
q
30
100
ns
DCMAX
Maximum G1 Duty Cycle
Figure 4
q
81
86
%
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: If IFB is taken below GND, it is clamped by an internal diode. This
pin handles input currents
≤ 100mA below GND without latch-up. In the
positive direction, it is not clamped to PVCC.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 4: The LTC1530 is tested in an op amp feedback loop which
regulates VSENSE or VOUT based on VCOMP = 2V for the error amplifier.
Note 5: The Open-loop DC gain and transconductance from the VFB pin to
the COMP pin are GERR and gmERR respectively. For fixed output voltage
versions, the actual open-loop DC gain and transconductance are GERR
and gmERR multiplied by the ratio 1.235/VOUT.
Note 6: The total voltage from the PVCC pin to the GND pin must be ≥8V
for the current limit protection circuit to be active.
Note 7: G1 and G2 begin to switch once PVCC is ≥ the undervoltage
lockout threshold voltage.
Note 8: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This current varies
with the LTC1530 operating frequency, supply voltage and the external
FETs used.
Note 9: The LTC1530 enters shutdown if COMP is pulled low.
Note 10: Slew rate is measured at the COMP pin on the transition from
shutdown to active mode.
The q denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. PVCC = 12V unless otherwise noted. (Note 3)
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