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参数资料
| 型号： | LTC1644IGN#TR |
| 厂商： | Linear Technology |
| 文件页数： | 9/24页 |
| 文件大小： | 447K |
| 描述： | IC CONTROLLER HOT SWAP 20-SSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | CompactPCI? |
| 内部开关： | 无 |
| 电源电压： | 3.3V，5V，±12V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | LTC1644IGNTR |
LTC1644
9
1644f
PI FU CTIO S
U
U
OFF/ON (Pin 5): Digital Input. Connect the CPCI BD_SEL#
signal to the OFF/ON pin. When the OFF/ON pin is pulled
low, the GATE pin is pulled high by a 65礎 current source
and the internal 12V and 12V switches are turned on.
When the OFF/ON pin is pulled high, the GATE pin will be
pulled to ground by a 225礎 current source and the 12V
and 12V switches turn off.
The OFF/ON pin is also used to reset the electronic circuit
breaker. If the OFF/ON pin is cycled high and low following
the trip of the circuit breaker, the circuit breaker is reset
and a normal power-up sequence will occur.
FAULT (Pin 6): Open-Drain Digital I/O. FAULT is pulled low
when a current limit fault is detected. Current limit faults
are ignored until the voltage at the TIMER pin is within 1V
of 12V
IN
. Once the TIMER cycle is complete, FAULT will
pull low and the chip latches off in the event of an
overcurrent fault. The chip will remain latched in the off
state until the OFF/ON pin is cycled high then low.
Forcing the FAULT pin low with an external pull-down will
cause the chip to be latched into the off state after a 45祍
deglitching time.
PWRGD (Pin 7): Open-Drain Digital Power Good Output.
Connect the CPCI HEALTHY# signal to the PWRGD pin.
PWRGD remains low while V
12VOUT
e 11.1V, V
3VOUT
e
2.9V, V
5VOUT
e 4.62V and V
EEOUT
d 10.5V. When any of
the supplies falls below its power good threshold voltage,
PWRGD will go high after a 10祍 deglitching time.
GND (Pin 8): Chip Ground.
RESETIN (Pin 9): Digital Input. Connect the CPCI PCI_RST#
signal to the RESETIN pin. Pulling RESETIN low will cause
RESETOUT to pull low.
RESETOUT (Pin 10): Open-Drain Digital Output. Connect
the CPCI LOCAL_PCI_RST# signal to the RESETOUT pin.
RESETOUT is the logical combination of RESETIN and
PWRGD.
DRIVE (Pin 11): Precharge Base Drive Output. Provides
base drive for an external NPN emitter-follower which in
turn biases the PRECHARGE node.
PRECHARGE (Pin 12): Precharge Monitor Input. An on-
chip error amplifier servos the DRIVE pin voltage to keep
the precharge node at 1V.
5V
IN
(Pin 13): 5V Supply Sense Input. An undervoltage
lockout circuit prevents the switches from turning on
when the voltage at the 5V
IN
pin is less than 2.48V. If no
5V input supply is available, tie the 5V
IN
to the 3V
IN
pin.
5V
SENSE
(Pin 14): 5V Current Limit Sense. With a sense
resistor placed in the supply path between 5V
IN
and
5V
SENSE
, the GATE pin voltage will be adjusted to maintain
a constant 51mV across the sense resistor and a constant
current through the switch while the TIMER pin is low. A
foldback feature reduces the current limit as the voltage at
the 5V
OUT
pin approaches GND.
When the TIMER pin is high, the circuit breaker function is
enabled. If the voltage across the sense resistor exceeds
55mV but is less than 150mV, the circuit breaker is tripped
after a 45祍 time delay. In the event the sense resistor
voltage exceeds 150mV, the circuit breaker trips immedi-
ately and the chip latches off. To disable the current limit,
5V
SENSE
and 5V
IN
can be shorted together.
GATE (Pin 15): High Side Gate Drive for the External 3.3V
and 5V N-Channels pass transistors. Requires an external
series RC network to compensate the current limit loop
and set the minimum ramp-up rate. During power up, the
slope of the voltage rise at the GATE is set by the 65礎
current source connected to 12V
IN
and the external ca-
pacitor connected to GND (C1, see Figure 1) or by the 3.3V
or 5V current limit and the bulk capacitance on the 3V
OUT
or 5V
OUT
supply lines (C
LOAD(5VOUT)
or C
LOAD(3VOUT)
, see
Figure 1). During power down, the slew rate of the GATE
voltage is set by the 225礎 current source connected to
GND and the external GATE capacitor (C1, see Figure 1).
The voltage at the GATE pin will be modulated to maintain
a constant current when either the 3V or 5V supplies go
into current limit while the TIMER pin is low. In the event
of a fault or an undervoltage condition, the GATE pin is
immediately pulled to GND.
3V
SENSE
(Pin 16): 3.3V Current Limit Set. With a sense
resistor placed in the supply path between 3V
IN
and
3V
SENSE
, the GATE pin voltage will be adjusted to maintain
a constant 51mV across the sense resistor and a constant
current through the switch while the TIMER pin is low. A
foldback feature reduces the current limit as the voltage at
the 3V
OUT
pin approaches GND.
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