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| 型号： | LTC1645IS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/24页 |
| 文件大小： | 329K |
| 描述： | IC CTLR HOT SWAP SEQ DUAL 8-SOIC |
| 标准包装： | 100 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 1.2 V ~ 12 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
8
LTC1645
1645fa
Power Supply Ramping
The power supplies on a board are controlled by placing
external N-channel pass transistors in the power paths as
shown in Figure 2. Consult Table 1 for a selection of
N-channel FETs suitable for use with the LTC1645. R
SENSE1
and R
SENSE2
provide current fault detection and R1 and R2
prevent high frequency oscillation. By ramping the gates
of the pass transistors up and down at a controlled rate,
the transient surge current (I = C " dv/dt) drawn from the
main backplane supply is limited to a safe value when the
board makes connection.
When power is first applied to the chip, the gates of the
N-channels (GATE1 and GATE2 pins) are pulled low. After
the ON pin is held above 0.8V for at least one timing cycle,
the voltage at GATE1 begins to rise with a slope equal to
dv/dt = 10礎/C1 (Figure 3), where C1 is the external
capacitor connected between the GATE1 pin and GND. If
the ON pin is brought above 2V (and the ON pin has been
held above 0.8V for at least one timing cycle), the voltage
at GATE2 begins to rise with a slope equal to dv/dt =
10礎/C2.
The ramp time for each supply is t = (V
CCn
" Cn)/10礎. If
the ON pin is pulled below 2V for GATE2 or 0.8V for GATE1
(but above 0.4V), a 40礎 current source is connected from
GATEn to GND, and the voltage at the GATEn pin will ramp
down, as shown in Figure 4.
Ringing
Good engineering practice calls for bypassing the supply
rail of any circuit. Bypass capacitors are often placed at the
supply connection of every active device, in addition to one
or more large value bulk bypass capacitors per supply rail.
If power is connected abruptly, the bypass capacitors slow
the rate of rise of voltage and heavily damp any parasitic
resonance of lead or trace inductance working against the
supply bypass capacitors.
The opposite is true for LTC1645 Hot Swap circuits on a
daughterboard. In most cases, on the powered side of the
N-channel FET switches (V
CCn
) there is no supply bypass
capacitor present. An abrupt connection, produced by
plugging a board into a backplane connector, results in a
fast rising edge applied to the V
CCn
line of the LTC1645.
APPLICATIO S I FOR ATIO
U
U
U
Figure 4. Supply Turning Off
Figure 3. Supply Turning On
Figure 2. Typical Hot Swap Connection
R
SENSE2
Q1
Q2
R2
10&
C2
C
TIMER
C
LOAD1
C
LOAD2
R1
10&
C1
12
1 2
3
8
9
6
5
11
7
13
14
10
4
V
CC1
ON
FAULT
SENSE1
GATE2
V
CC2
V
CC2
V
CC1
V
OUT2
V
OUT1
LTC1645
(14-LEAD)
TIMER
GND
COMP
+
COMPOUT
FB
SENSE2
GATE1
1645 F02
RESET
+
+
R
SENSE1
V
CCn
V
OUTn
V
CCn
+ V
GATE
1645 F03
t
1
t
2
GATEn
SLOPE = 10礎/C
n
V
CCn
V
OUTn
V
CCn
+ V
GATE
1645 F04
t
3
t
4
GATEn
SLOPE = 40礎/C
n
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