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参数资料
| 型号： | LTC1698IS#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR ISO PWM CM 16-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 400kHz |
| 电源电压： | 6 V ~ 12.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
LTC1698
APPLICATIO S I FOR ATIO
Undervoltage Lockout
In UVLO (low V DD voltage) the drivers FG and CG are shut
off and the pins OPTODRV, V AUX , PWRGD and I COMP are
forced low. The LTC1698 allows the bandgap and the
internal bias currents to reach their steady-state values
before releasing UVLO. Typically, this happens when V DD
reaches approximately 4.0V. Beyond this threshold, the
drivers start switching. The OPTODRV, V AUX , PWRGD and
I COMP pins return to their normal values and the chip is
fully functional. However, if the V DD voltage is less than 7V,
the OPTODRV and V AUX current sourcing capabilities are
limited. See the OPTO driver graphs in the Typical Perfor-
mance Characteristics section.
V DD Regulator
supply requirement. Under start-up conditions, it must be
small enough to power up instantaneously, enabling the
LTC1698 to regulate the feedback loop. Using a larger
capacitor requires evaluation of the start-up performance.
SYNC Input
Figure 3 shows the synchronous forward converter appli-
cation. The primary controller LT3781 runs at a fixed
frequency and controls MOSFETs Q1 and Q2. The second-
ary controller LTC1698 controls MOSFETs Q3 and Q4. An
inexpensive, small-size pulse transformer T2 synchro-
nizes the primary and the secondary controllers. Figure 4
shows the pulse transformer timing waveforms. When the
LT3781 synchronization output SG goes low, MOSFET
L1
The bias supply for the LTC1698 is generated by peak
rectifying the isolated transformer secondary winding. As
TG
Q1
Q4
CG
V OUT
shown in Figure 2, the zener diode Z1 is connected from
base of Q5 to ground such that the emitter of Q5 is
regulated to one diode drop below the zener voltage. R Z is
V IN
PRIMARY
CONTROLLER
LT3781
D1
?
D2
?
T1
SECONDARY
CONTROLLER
LTC1698
C OUT
selected to bring Z1 into conduction and also provide base
current to Q5. A resistor (on the order of a few hundred
SG
BG
Q2
Q3
FG SYNC
ohms), in series with the base of Q5, may be required to
surpress high frequency oscillations depending on Q5’s
?
?
1698 F03
selection. A power MOSFET can also be used by increasing
the zener diode value to offset the drop of the gate-to-
source voltage. V DD supply current varies linearly with the
supply voltage, driver load and clock frequency. A 4.7 μ F
PRIMARY
C SG
T2
C SYNC
R SYNC
SECONDARY
bypass capacitor for the V DD supply is sufficient for most
applications. This capacitor must be large enough to
provide a stable DC voltage to meet the LTC1698 V DD
V SECONDARY
1 ?
D3
ISOLATION BARRIER
Figure 3. Synchronization Using Pulse Transformer
TG
BG
SG
0.47 μ F
R Z
2k
Z1
10V
R B *
Q5
FZT690
4.7 μ F
V DD
SYNC
FG
CG
*R B IS OPTIONAL, SEE TEXT
1698 F02
Figure 4. Primary Side and Secondary Side
1698 F04
Figure 2. V DD Regulator
Synchronization Waveforms
1698f
10
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