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参数资料
| 型号： | LTC1698IS#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR ISO PWM CM 16-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 400kHz |
| 电源电压： | 6 V ~ 12.6 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
LTC1698
PI FU CTIO S
V DD (Pin 1): Power Supply Input. For isolated applica-
tions, a simple rectifier from the power transformer is
used to power the chip. This pin powers the opto driver,
the V AUX supply and the FG and CG drivers. An internal 5V
regulator powers the remaining circuitry. V DD requires an
external 4.7 μ F bypass capacitor.
CG (Pin 2): Catch Gate Driver. If SYNC slews positive, CG
pulls high to drive an external N-channel MOSFET. CG
draws power from the V DD pin and swings between V DD
and PGND.
PGND (Pin 3): Power Ground. Connect PGND to a low
impedance ground plane in close proximity to the ground
terminal of the external current sensing resistor.
GND (Pin 4): Logic and Signal Ground. GND is referenced
to the internal low power circuitry. Careful board layout
techniques must be used to prevent corruption of signal
ground reference. Connect GND and PGND together di-
rectly at the LTC1698.
OPTODRV (Pin 5): Optocoupler Driver Output. This pin
drives a ground referenced optocoupler through an exter-
nal resistor. If V FB is low, OPTODRV pulls low. If V FB is
high, OPTODRV pulls high. This optocoupler driver has a
DC gain of 5. During overvoltage or overcurrent condi-
tions, OPTODRV pulls high. The output is capable of
sourcing 10mA of current and will drive an external 0.1 μ F
capacitive load and is short-circuit protected.
V COMP (Pin 6): Error Amplifier Output. This error amplifier
is able to drive more than 2k ? and 100pF of load. The
internal diode connected from V FB to V COMP reduces
OPTODRV recovery time under start-up conditions.
MARGIN (Pin 7): Current Input to Adjust the Output
Voltage Linearly. The MARGIN pin connects to an internal
16.5k resistor. The other end of this resistor is regulated
to 1.65V. Connecting MARGIN to a 3.3V logic supply
sources 100 μ A of current into the chip and moves the
output voltage 5% higher. Connecting MARGIN to 0V
sinks 100 μ A out of the pin and moves the regulated output
voltage 5% lower. The MARGIN pin voltage does not affect
the PWRGD and OVPIN trip points.
V FB (Pin 8): Feedback Voltage. V FB senses the regulated
output voltage through an external resistor divider. The
V FB pin is servoed to the reference voltage of 1.233V under
closed-loop conditions. An RC network from V FB to V COMP
compensates the feedback loop. If V FB goes low, V COMP
pulls high and OPTODRV goes low.
OVPIN (Pin 9): Overvoltage Input. OVPIN is a high imped-
ance input to an internal comparator. The threshold of this
comparator is set to 1.233V. If the OVPIN potential is
higher than the threshold voltage, OPTODRV pulls high
immediately. Use an external RC lowpass filter to prevent
noisy signals from triggering this comparator.
PWRGD (Pin 10): Power Good Output. This is an open-
drain output. PWRGD floats if V FB is above 94% of the
nominal value for more than 2ms. PWRGD pulls low if V FB
is below 94% of the nominal value for more than 1ms. The
PWRGD threshold is independent of the MARGIN pin
potential.
I SNSGND (Pin 11): Current Sense Ground. Connect to the
positive side of the sense resistor, normally grounded.
I SNS (Pin 12): Current Sense Input. Connect to the nega-
tive side of the sense resistor through an external RC
lowpass filter. This pin normally sees a negative voltage,
which is proportional to the average load current. If
current limit is exceeded, OPTODRV pulls high.
I COMP (Pin 13): Current Amplifier Output. An RC network
at this pin compensates the current limit feedback loop.
Referencing the RC to V OUT controls output voltage over-
shoot on start-up. This pin can float if current limit loop
compensation is not required.
V AUX (Pin 14): Auxiliary 3.3V Logic Supply. This pin
requires a 0.1 μ F or greater bypass capacitor. This auxiliary
power supply can power external devices and sources
10mA of current. Internal current limiting is provided.
SYNC (Pin 15): Drivers Synchronization Input. A negative
voltage slew at SYNC forces FG to pull high and CG to pull
low. A positive voltage slew at SYNC resets the FG pin and
CG pulls high. If SYNC loses its synchronization signal for
more than the driver disable time-out interval, both the
forward and catch drivers output are forced low. The SYNC
circuit accepts pulse and square wave signals. The mini-
mum pulse width is 75ns. The synchronization frequency
range is between 50kHz to 400kHz.
FG (Pin 16): Forward Gate Driver. If SYNC slews negative,
FG goes high. FG draws power from V DD and swings
between V DD and PGND.
1698f
7
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