参数资料
型号: LTC1735CGN#TRPBF
厂商: Linear Technology
文件页数: 26/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16-SSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 335kHz
占空比: 99.4%
电源电压: 4 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 85°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 带卷 (TR)
LTC1735
APPLICATIO S I FOR ATIO
Next verify the minimum on-time of 200ns is not violated.
The minimum on-time occurs at maximum V IN :
C IN is chosen for an RMS current rating of at least 2.5A at
temperature. C OUT is chosen with an ESR of 0.02 ? for low
output ripple. The output ripple in continuous mode will be
t ON ( MIN ) =
V OUT
V IN ( MAX ) f
=
1 . 8 V
22 V ( 300 kHz )
= 273 ns
highest at the maximum input voltage. The worst-case
output voltage ripple due to ESR is approximately:
R 1 ( MAX ) = 24 k ?
? 2 . 4 V – V OUT ?
= 24 k ?
? = 32 k
( 5 ) 2 [ 1 + ( 0 . 005 )( 50 ° C – 25 ° C ) ] ( 0 . 035 ? )
P MAIN =
+ 1 . 7 ( 22 V ) ( 5 A )( 100 pF )( 300 kHz )
Sincetheoutputvoltageisbelow2.4Vtheoutputresistive
divider will need to be sized to not only set the output
voltage but also to absorb the sense pin current.
? 0 . 8 V ?
?
? 0 . 8 V ?
? 2 . 4 V – 1 . 8 V ?
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412ADY results
in R DS(ON) = 0.035 ? , C RSS = 100pF. At maximum input
voltage with T(estimated) = 50 ° C:
1 .8 V
22 V
2
= 204 mW
Because the duty cycle of the bottom MOSFET is much
greater than the top, a larger MOSFET, Siliconix Si4410DY,
(R DS(ON) = 0.02 ? ) is chosen. The power dissipation in the
bottom MOSFET, again assuming T A = 50 ° C, is:
V ORIPPLE = R ESR ( ? I L ) = 0 . 02 ? ( 2 . 3 A ) = 46 mV P ? P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1735. These items are also illustrated graphically in
the layout diagram of Figure 12. Check the following in
your layout:
1) Are the signal and power grounds segregated? The
LTC1735 PGND pin should tie to the ground plane close to
the input capacitor(s). The SGND pin should then connect
to PGND, and all components that connect to SGND
should make a single point tie to the SGND pin. The
synchronous MOSFET source pins should connect to the
input capacitor(s) ground.
2) Does the V OSENSE pin connect directly to the feedback
resistors? The resistive divider R1, R2 must be connected
between the (+) plate of C OUT and signal ground. The 47pF
to 100pF capacitor should be as close as possible to the
LTC1735. Be careful locating the feedback resistors too far
away from the LTC1735. The V OSENSE line should not be
routed close to any other nodes with high slew rates.
3) Are the SENSE – and SENSE + leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE + and SENSE – should be as close as possible to the
LTC1735. Ensure accurate current sensing with Kelvin
P SYNC =
22 V – 1. 8 V
22 V
( 5 A ) ( 2 1 . 1 ) ( 0 . 02 ? )
connections as shown in Figure 13. Series resistance can
be added to the SENSE lines to increase noise rejection.
= 505 mW
Thanks to current foldback, the bottom MOSFET dissipa-
tion in short-circuit will be less than under full load
conditions.
4) Does the (+) terminal of C IN connect to the drain of the
topside MOSFET(s) as closely as possible? This capacitor
provides the AC current to the MOSFET(s).
5) Is the INTV CC decoupling capacitor connected closely
between INTV CC and the power ground pin? This capaci-
tor carries the MOSFET driver peak currents. An addi-
tional 1 μ F ceramic capacitor placed immediately next to
1735fc
26
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