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参数资料
| 型号： | LTC1736IG#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/28页 |
| 文件大小： | 0K |
| 描述： | IC SW REG STEP-DONW SYNC 24-SSOP |
| 标准包装： | 1,800 |
| 应用： | 转换器，Intel Pentium? II，III |
| 输入电压： | 3.5 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 0.93 V ~ 2 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 带卷 (TR) |
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LTC1736
PI FU CTIO S
C OSC (Pin 1): External capacitor C OSC from this pin to
ground sets the operating frequency.
RUN/SS (Pin 2): Combination of Soft-Start and Run
Control Inputs. A capacitor to ground at this pin sets the
ramp time to full output current. The time is approximately
1.25s/ μ F. Forcing this pin below 1.5V causes the device to
be shut down. In shutdown all functions are disabled.
Latchoff overcurrent protection is also invoked via this pin
as described in the Applications Information section.
I TH (Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 2.4V.
FCB (Pin 4): Forced Continuous/Synchronization Input.
Tie this pin to ground for continuous synchronous opera-
tion, to a resistive divider from the secondary output when
using a secondary winding, or to INTV CC to enable Burst
Mode operation at low load currents. Clocking this pin with
a signal above 1.5V P-P disables Burst Mode operation but
allows cycle skipping at low load currents and synchro-
nizes the internal oscillator with the external clock.
SGND (Pin 5): Small-Signal Ground. All small-signal
components such as C OSC , C SS plus the loop compensa-
tion resistors and capacitor(s) should single-point tie to
this pin. This pin should, in turn, connect to PGND.
PGOOD (Pin 6): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on the V OSENSE pin is
not within ± 7.5% of its set point.
SENSE – (Pin 7): The (–) Input to the Current Comparator.
SENSE + (Pin 8): The (+) Input to the Current Comparator.
Built-in offsets between SENSE – and SENSE + pins in
conjunction with R SENSE set the current trip threshold.
V FB (Pin 9): Divided Down V OSENSE Voltage Feeding the
Error Amplifier of the Regulator. The VID inputs program
a resistive divider between V OSENSE and SGND; the tap
point on the divider is V FB . The voltage on V FB is 0.8V when
the output is in regulation. This pin can be bypassed to
SGND with 50pF to 100pF.
V OSENSE (Pin 10): Receives the remotely sensed feedback
voltage from the output.
VID0 to VID4 (Pins 11 to 15): Digital Inputs for controlling
the output voltage from 0.925V to 2.0V. Table 1 specifies
the V OSENSE voltages for the 32 combinations of digital
inputs. The LSB (VID0) represents 50mV increments in
the upper voltage range (2.00V to 1.30V) and 25mV
increments in the lower voltage range (1.275V to 0.925V).
Logic Low = GND, Logic High = VIDV CC or Float.
VIDV CC (Pin 16): VID Input Supply Voltage. Can range
from 2.7V to 7V. Typically this pin is tied to INTV CC .
EXTV CC (Pin 17): Input to the Internal Switch Connected
to INTV CC . This switch closes and supplies V CC power
whenever EXTV CC is higher than 4.7V. See EXTV CC con-
nection in the Applications Information section. Do not
exceed 7V to this pin and ensure EXTV CC ≤ V IN .
PGND (Pin 18): Driver Power Ground. This pin connects
to the source of the bottom N-channel MOSFET, the anode
of the Schottky diode and the (–) terminal of C IN .
BG (Pin 19): High Current Gate Drive for Bottom
N-Channel MOSFET. Voltage swing at this pin is from
ground to INTV CC .
INTV CC (Pin 20): Output of the Internal 5.2V Regulator and
EXTV CC Switch. The driver and control circuits are pow-
ered from this voltage. Decouple to power ground with a
1 μ F ceramic capacitor placed directly adjacent to the IC
together with a minimum of 4.7 μ F tantalum or other low
ESR capacitor.
V IN (Pin 21): Main Supply Pin. This pin must be closely
decoupled to power ground.
SW (Pin 22): Switch Node Connection to Inductor and
Bootstrap Capacitor. Voltage swing at this pin is from a
Schottky diode (external) voltage drop below ground to
V IN .
BOOST (Pin 23): Supply to Topside Floating Driver. The
bootstrap capacitor is returned to this pin. Voltage swing
at this pin is from a diode drop below INTV CC to V IN +
INTV CC .
TG (Pin 24): High Current Gate Drive for Top N-Channel
MOSFET. This is the output of a floating driver with a
voltage swing equal to INTV CC superimposed on the
switch node voltage SW.
7
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