参数资料
型号: LTC1741CFW
厂商: Linear Technology
文件页数: 7/20页
文件大小: 0K
描述: IC ADC 12BIT 65MSPS 48-TSSOP
标准包装: 39
位数: 12
采样率(每秒): 65M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 1.38W
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 48-TSSOP
包装: 管件
输入数目和类型: 2 个单端,双极;1 个差分,双极
产品目录页面: 1349 (CN2011-ZH PDF)
15
LTC1741
1741f
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1741 is 65Msps. For
the ADC to operate properly the encode signal should have
a 50% (
±5%) duty cycle. Each half cycle must have at least
7.3ns for the ADC internal circuitry to have enough settling
time for proper operation. Achieving a precise 50% duty
cycle is easy with differential sinusoidal drive using a
transformer or using symmetric differential logic such as
PECL or LVDS. When using a single-ended encode signal
asymmetric rise and fall times can result in duty cycles that
are far from 50%.
At sample rates slower than 65Msps the duty cycle can
vary from 50% as long as each half cycle is at least 7.3ns.
The lower limit of the LTC1741 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC1741 is 1Msps.
DIGITAL OUTPUTS
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
APPLICATIO S I FOR ATIO
WU
UU
Driving the Encode Inputs
The noise performance of the LTC1741 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
The encode inputs have a common mode range of 1.8V to
VDD. Each input may be driven from ground to VDD for
single-ended drive.
LTC1741
1741 F09
OVDD
VDD
0.1
F
43
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V TO
VDD
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
Figure 9. Equivalent Circuit for a Digital Output Buffer
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