参数资料
型号: LTC1876EG#PBF
厂商: Linear Technology
文件页数: 17/36页
文件大小: 0K
描述: IC REG CTRLR BST PWM CM 36-SSOP
标准包装: 37
系列: PolyPhase®
PWM 型: 电流模式
输出数: 3
频率 - 最大: 360kHz
占空比: 99.4%
电源电压: 3.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-SSOP(0.209",5.30mm 宽)
包装: 管件
产品目录页面: 1333 (CN2011-ZH PDF)
LTC1876
APPLICATIO S I FOR ATIO
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramic voltage
coefficients are very high and may have audible piezoelec-
tric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics’ higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22 μ F or two to three 10 μ F ceramic capaci-
tors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also con-
sider parallel ceramic and high quality electrolytic capaci-
tors as an effective means of achieving ESR and bulk
capacitance goals.
In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle V OUT /V IN . To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current of one channel must
be used. The maximum RMS capacitor current is given by:
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Remember that protection fuse
resistance, battery resistance and PC board trace resis-
tance losses are also reduced due to the reduced peak
currents in a multiphase system. The overall benefit of a
multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The drains of the two top MOSFETS
should be placed within 1cm of each other and share a
common C IN (s). Separating the drains and C IN may pro-
duce undesirable voltage and current resonances at V IN .
For the boost regulator, the ripple requirement for the
input capacitor is less stringent. If the supply to the
regulator is obtained from one of the LTC1876 step-down
outputs, a 1 μ F to 4.7 μ F ceramic capacitor is sufficient.
However, if the step-down output is within close proximity
(< 1cm) to the boost supply input, there is no need for the
capacitor.
C OUT Selection
[ V ( V
) ]
C IN Re quired I RMS ≈ I MAX
OUT IN ? V OUT
V IN
1 / 2
The selection of C OUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
For the step-down regulators, the output ripple ( ? V OUT ) is
determined by:
? V OUT L ? ESR +
8 fC OUT ?
This  formula  has  a  maximum  at  V IN =  2V OUT ,  where
I RMS = I OUT /2. This simple worst case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
≈ ? I
?
?
1 ?
?
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
The benefit of the LTC1876 multiphase controllers can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switch on at the
same time. The total RMS power lost is lower when both
Where f = operating frequency, C OUT = output capacitance,
and ? L = ripple current in the inductor. The output ripple is
highest at maximum input voltage since ? I L increases
with input voltage. With ? I L = 0.4I OUT(MAX) the output
ripple will typically be less than 50mV at max V IN assum-
ing:
C OUT Recommended ESR < 2 R SENSE
and C OUT > 1/(8fR SENSE )
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran-
tees that the output capacitance does not significantly
1876fa
17
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