参数资料
型号: LTC1877EMS8#TR
厂商: Linear Technology
文件页数: 8/18页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.6A 8MSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 10 V
输入电压: 2.65 V ~ 10 V
PWM 型: 电流模式,混合
频率 - 开关: 550kHz
电流 - 输出: 600mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-MSOP
LTC1877
OPERATION
(Refer to Functional Diagram)
The LTC1877 uses a constant-frequency, current mode
step-down architecture. Both the main (P-channel MOS-
FET) and synchronous (N-channel MOSFET) switches are
internal. During normal operation, the internal top power
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the current comparator,
I COMP , resets the RS latch. The peak inductor current at
which I COMP resets the RS latch is controlled by the volt-
age on the I TH pin, which is the output of error ampli?er
EA. The V FB pin, described in the Pin Functions section,
allows EA to receive an output feedback voltage from an
external resistive divider. When the load current increases,
it causes a slight decrease in the feedback voltage relative
to the 0.8V reference, which in turn, causes the I TH voltage
to increase until the average inductor current matches the
new load current. While the top MOSFET is off, the bottom
MOSFET is turned on until either the inductor current starts
to reverse as indicated by the current reversal comparator
I RCMP , or the beginning of the next clock cycle.
Comparator OVDET guards against transient overshoots
> 6.25% by turning the main switch off and keeping it off
until the fault is removed.
Burst Mode Operation
The LTC1877 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to V IN or connect it to a logic
high (V SYNC/MODE > 1.5V). To disable Burst Mode opera-
tion and enable PWM pulse-skipping mode, connect the
SYNC/MODE pin to GND. In this mode, the ef?ciency is
lower at light loads, but becomes comparable to Burst
Mode operation when the output load exceeds 50mA. The
advantage of pulse-skipping mode is lower output ripple
and less interference to audio circuitry.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 250mA,
even though the voltage at the I TH pin indicates a lower
value. The voltage at the I TH pin drops when the inductor’s
average current is greater than the load requirement. As the
I TH voltage drops below approximately 0.55V, the BURST
comparator trips, causing the internal sleep line to go
then disconnected from the output of the EA ampli?er and
parked a diode voltage above ground.
In sleep mode, both power MOSFETs are held off and a
majority of the internal circuitry is partially turned off,
reducing the quiescent current to 10μA. The load current
is now being supplied solely from the output capacitor.
When the output voltage drops, the I TH pin reconnects
to the output of the EA ampli?er and the top MOSFET is
again turned on and this process repeats.
Short-Circuit Protection
When the output is shorted to ground, the frequency of
the oscillator is reduced to about 80kHz, one-seventh the
nominal frequency. This frequency foldback ensures that
the inductor current has ample time to decay, thereby
preventing runaway. The oscillator’s frequency will progres-
sively increase to 550kHz (or the synchronized frequency)
when V FB rises above 0.3V.
Frequency Synchronization
A phase-locked loop (PLL) is available on the LTC1877 to
allow the internal oscillator to be synchronized to an external
source connected to the SYNC/MODE pin. The output of
the phase detector at the PLL LPF pin operates over a 0V
to 2.4V range corresponding to 400kHz to 700kHz. When
locked, the PLL aligns the turn-on of the top MOSFET to
the rising edge of the synchronizing signal.
When the LTC1877 is clocked by an external source, Burst
Mode operation is disabled; the LTC1877 then operates in
PWM pulse-skipping mode. In this mode, when the output
load is very low, current comparator I COMP may remain
tripped for several cycles and force the main switch to stay
off for the same number of cycles. Increasing the output
load slightly allows constant-frequency PWM operation
to resume. This mode exhibits low output ripple as well
as low audio noise and reduced RF interference while
providing reasonable low current ef?ciency.
Frequency synchronization is inhibited when the feedback
voltage V FB is below 0.6V. This prevents the external clock
from interfering with the frequency foldback for short-
circuit protection.
high and forces off both power MOSFETs. The I TH pin is
1877fb
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