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参数资料
| 型号： | LTC1879EGN#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1.2A 16SSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 10 V |
| 输入电压： | 2.65 V ~ 10 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 550kHz |
| 电流 - 输出： | 1.2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-SSOP |
LTC1879
APPLICATIO S I FOR ATIO
Where ρ 1, ρ 2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1879 circuits: supply quiescent currents and
I 2 R losses. The supply quiescent current loss dominates
the efficiency loss at very low load current whereas the I 2 R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 7.
1. The supply quiescent current is due to two compo-
nents: the DC bias current as given in the Electrical
Characteristics and the internal main switch and syn-
chronous switch gate charge currents. The gate charge
current results from switching the gate capacitance of
the internal power MOSFET switches. Each time the
gate is switched from high to low to high again, a
packet of charge dQ moves from PV IN to ground. The
resulting dQ/dt is the current out of PV IN that is typically
larger than the DC bias current. In continuous mode,
I GATECHG = f(Q T + Q B ) where Q T and Q B are the gate
charges of the internal top and bottom switches. Both
the DC bias and gate charge losses are proportional to
supply voltage and thus their effects will be more
pronounced at higher supply voltages.
2. I 2 R losses are calculated from the resistances of the
internal switches R SW and external inductor R L . In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into SW pins is a function of both top
and bottom MOSFET R DS(ON) and the duty cycle (DC) as
follows:
R SW = (R DS(ON)TOP )(DC) + (R DS(ON)BOT )(1 – DC)
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I 2 R losses, simply add R SW
to R L and multiply by the square of the average output
current.
Other losses including C IN and C OUT ESR dissipative
losses, MOSFET switching losses and inductor core losses
generally account for less than 2% total additional loss.
Thermal Considerations
In most applications, the LTC1879 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC1879 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150 ° C, both power switches
1
0.1
0.01
0.001
V IN = 6V
V OUT = 3.3V
L = 6.8 μ H
Burst Mode OPERATION
will be turned off and the SW nodes will become high
impedance.
To avoid the LTC1879 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. Normally,
some iterative calculation is required to determine a rea-
sonably accurate value. The temperature rise is given by:
0.0001
0.1
1
10 100
LOAD CURRENT (mA)
1000
T R = P ? θ JA
where P is the power dissipated by the regulator and θ JA
1879 F07
Figure 7. Power Lost vs Load Current
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature is given by:
T J = T A + T R
1879f
13
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