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| 型号： | LTC1879EGN |
| 厂商： | Linear Technology |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 1.2A 16SSOP |
| 标准包装： | 100 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 10 V |
| 输入电压： | 2.65 V ~ 10 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 550kHz |
| 电流 - 输出： | 1.2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 16-SSOP |
LTC1879
APPLICATIO S I FOR ATIO
0.8V ≤ V OUT ≤ 10V
R LP
V FB
R1
2.4V
PLL_LPF
C LP
LTC1879
R2
SYNC/
MODE
DIGITAL
SGND
1879 F04
PHASE/
FREQUENCY
DETECTOR
VCO
Figure 4. Setting the LTC1879 Output Voltage
Phase-Locked Loop and Frequency Synchronization
The LTC1879 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the MOSFET turn-on to be locked to the rising edge
of an external frequency source. The frequency range of
the voltage-controlled oscillator is 350kHz to 750kHz. The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector will not
lock up on input frequencies close to the harmonics of the
VCO center frequency. The PLL hold-in range ? f H is equal
to the capture range, ? f H = ? f C = ± 200kHz.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
filter network on the PLL_LPF pin. The relationship be-
tween the voltage on the PLL_LPF pin and operating
frequency is shown in Figure 5. A simplified block diagram
is shown in Figure 6.
1000
900
800
700
600
500
400
300
200
100
1879 F06
Figure 6. Phase-Locked Loop Block Diagram
If the external frequency (V SYNC/MODE ) is greater than
550kHz, the center frequency, current is sourced continu-
ously, pulling up the PLL_LPF pin. When the external
frequency is less than 550kHz, current is sunk continu-
ously, pulling down the PLL_LPF pin. If the external and
internal frequencies are the same but exhibit a phase
difference, the current sources turn on for an amount of
time corresponding to the phase difference. Thus the
voltage on the PLL_LPF pin is adjusted until the phase and
frequency of the external and internal oscillators are
identical. At this stable operating point the phase com-
parator output is open and the filter capacitor C LP holds the
voltage.
The loop filter components C LP and R LP smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C LP and R LP determine how fast the loop
acquires lock. Typically R LP = 10k and C LP is 2200pF to
0.01 μ F. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillation frequency by a DC
voltage on the V PLLLPF pin.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
0
0
0.5
1
V PLLLPF (V)
1.5
2
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
1879 F05
Figure 5. Relationship Between Oscillator Frequency
and Voltage at PLL_LPF Pin
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – ( ρ 1 + ρ 2 + ρ 3 + ...)
1879f
12
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