参数资料
型号: LTC2163IUK#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封装: 7 X 7 MM, LEAD FREE, PLASTIC, MO-220WKKD-2, QFN-48
文件页数: 1/36页
文件大小: 663K
代理商: LTC2163IUK#PBF
LTC2165/LTC2164/LTC2163
1
216543f
Typical applicaTion
DescripTion
16-Bit, 125/105/80Msps
Low Power ADCs
The LTC2165/LTC2164/LTC2163 are sampling 16-bit A/D
converters designed for digitizing high frequency, wide
dynamic range signals. They are perfect for demanding
communications applications with AC performance that
includes 76.8dB SNR and 90dB spurious free dynamic
range (SFDR). Ultralow jitter of 0.07psRMS allows unders-
amplingofIFfrequencieswithexcellentnoiseperformance.
DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.4LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENCinputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
2-Tone FFT, fIN = 70MHz and 69MHz
FeaTures
applicaTions
n
76.8dB SNR
n
90dB SFDR
n
Low Power: 194mW/163mW/108mW
n
Single 1.8V Supply
n
CMOS, DDR CMOS, or DDR LVDS Outputs
n
Selectable Input Ranges: 1VP-P to 2VP-P
n
550MHz Full Power Bandwidth S/H
n
Optional Data Output Randomizer
n
Optional Clock Duty Cycle Stabilizer
n
Shutdown and Nap Modes
n
Serial SPI Port for Configuration
n
48-Pin (7mm × 7mm) QFN Package
n
Communications
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multichannel Data Acquisition
n
Nondestructive Testing
FREQUENCY (MHz)
0
–100
–110
–120
–70
–60
–80
–90
AMPLITUDE
(dBFS) –50
–30
–40
–20
–10
0
10
20
30
40
50
60
2165 TA01b
S/H
OUTPUT
DRIVERS
16-BIT
ADC CORE
CLOCK
CONTROL
D15
D0
125MHz
CLOCK
ANALOG
INPUT
2165 TA01a
CMOS, DDR
CMOS OR
DDR LVDS
OUTPUTS
1.8V
VDD
1.8V
OVDD
GND
OGND
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