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参数资料
| 型号： | LTC2171IUKG-14#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SER/PAR 40M 52-QFN |
| 标准包装： | 2,000 |
| 位数： | 14 |
| 采样率（每秒）： | 45M |
| 数据接口： | Serial LVDS |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 293mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-WFQFN 裸露焊盘 |
| 供应商设备封装： | 52-QFN（7x8） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 Differential; 2 Single-Ended |
| 配用： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
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LTC2172-14/
LTC2171-14/LTC2170-14
26
21721014fb
applicaTions inForMaTion
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be
written to the register set by the address bits (A6:A0).
If the R/W bit is high, data in the register set by the
address bits (A6:A0) will be read back on the SDO pin
(see the Timing Diagrams section). During a readback
command the register is not updated and data on SDI
is ignored.
The SDO pin is an open-drain output that pulls to ground
with a 200 impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed.Table4showsamapofthemodecontrolregisters.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
D5
D4
D3
D2
D1
D0
RESET
X
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This bit is
automatically set back to zero after the reset is complete at the end of the SPI write command. The reset register is write only.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_4
NAP_3
NAP_2
NAP_1
Bit 7
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.
Bit 6
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 5
TWOSCOMP
Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Bits 4-0
SLEEP:NAP_4:NAP_1
Sleep/Nap Mode Control Bits
00000 = Normal Operation
0XXX1 = Channel 1 in Nap Mode
0XX1X = Channel 2 in Nap Mode
0X1XX = Channel 3 in Nap Mode
01XXX = Channel 4 in Nap Mode
1XXXX = Sleep Mode. All Channels Are Disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2172-12 | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65Msps/40Msps/25Msps Low Power Quad ADCs |
| LTC2172-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Quad 14-Bit, 125Msps ADC with Integrated Drivers |
| LTC2172CUKG-12#PBF | 功能描述:IC ADC 12BIT SER/PAR 65M 52-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| LTC2172CUKG-12#TRPBF | 功能描述:IC ADC 12BIT SER/PAR 65M 52-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2172CUKG-12PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 65Msps/40Msps/25Msps Low Power Quad ADCs |
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