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参数资料
| 型号： | LTC2202CUK#TRPBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 16-Bit, 10Msps ADC; Package: QFN; No of Pins: 48; Temperature Range: 0°C to +70°C |
| 中文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封装： | 7 X 7 MM, LEAD FREE, PLASTIC, MO-220WKKD-2, QFN-48 |
| 文件页数： | 11/32页 |
| 文件大小： | 1450K |
| 代理商： | LTC2202CUK#TRPBF |
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LTC2203/LTC2202
19
22032fd
CONVERTER OPERATION
The LTC2203/LTC2202 are CMOS pipelined multistep con-
verters with a front-end PGA. As shown in Figure 1, the
converter has ve pipelined ADC stages; a sampled analog
inputwillresultinadigitizedvaluesevencycleslater(seethe
Timing Diagram section). The analog input is differential
for improved common mode noise immunity and to
maximize the input range. Additionally, the differential
input drive will reduce even order harmonics of the
sample-and-hold circuit.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplied and
output by the residue amplier. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
The phase of operation is determined by the state of the
CLK input pin.
When CLK is high, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that CLK transitions from high to low, the volt-
age on the sample capacitors is held. While CLK is low,
the held input voltage is buffered by the S/H amplier
which drives the rst pipelined ADC stage. The rst stage
acquires the output of the S/H amplier during the low
phase of CLK. When CLK goes back high, the rst stage
produces its residue which is acquired by the second stage.
At the same time, the input S/H goes back to acquiring
the analog input. When CLK goes low, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fth stage for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2203/
LTC2202 CMOS differential sample and hold. The differ-
ential analog inputs are sampled directly onto sampling
capacitors (CSAMPLE) through NMOS transitors. The
capacitors shown attached to each input (CPARASITIC) are
the summation of all other capacitance associated with
each input.
During the sample phase when CLK is high, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When CLK transitions from high to low, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when CLK is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As CLK
transitions from low to high, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time at the input of
the converter. If the change between the last sample and
Figure 2. Equivalent Input Circuit
LTC2203/LTC2202
CLK
22032 F02
VDD
RPARASITIC
3Ω
RPARASITIC
3Ω
AIN+
AIN–
CPARASITIC
1.4pF
CPARASITIC
1.4pF
CSAMPLE
9.1pF
CSAMPLE
9.1pF
RON
20Ω
RON
20Ω
APPLICATIONS INFORMATION
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2202IUK#PBF | 16-Bit, 10Msps ADC; Package: QFN; No of Pins: 48; Temperature Range: -40°C to +85°C |
| LTC2202IUK#TRPBF | 16-Bit, 10Msps ADC; Package: QFN; No of Pins: 48; Temperature Range: -40°C to +85°C |
| LTC2203CUK#PBF | 16-Bit, 25Msps ADC; Package: QFN; No of Pins: 48; Temperature Range: 0°C to +70°C |
| LTC2203CUK#TRPBF | 16-Bit, 25Msps ADC; Package: QFN; No of Pins: 48; Temperature Range: 0°C to +70°C |
| LTC2203IUK#PBF | 16-Bit, 25Msps ADC; Package: QFN; No of Pins: 48; Temperature Range: -40°C to +85°C |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2202IUK | 制造商:Linear Technology 功能描述:ADC Single Pipelined 10Msps 16-bit Parallel 48-Pin QFN EP |
| LTC2202IUK#PBF | 功能描述:IC ADC 16-BIT 10MSPS 48-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
| LTC2202IUK#TRPBF | 功能描述:IC ADC 16-BIT 10MSPS 48-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2202UK | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 25Msps/10Msps ADCs |
| LTC2203 | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 25Msps/10Msps ADCs |
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