参数资料
型号: LTC2202I
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封装: 7 X 7 MM, PLASTIC, MO-220-WKKD-2, QFN-48
文件页数: 15/26页
文件大小: 1118K
代理商: LTC2202I
PREP
ARED
FOR
LTC2203/LTC2202
22
22032p
Output Clock
The ADC has a delayed version of the CLK input available
as a digital output. Both a noninverted version, CLKOUT+
and an inverted version CLKOUTare provided. The
CLKOUT+/CLKOUTcan be used to synchronize the con-
verter data to the digital system. This is necesary when
using a sinusoidal clock. Data can be latched on the ris-
ing edge of CLKOUT+ or the falling edge of CLKOUT–.
CLKOUT+ falls and CLKOUT– rises as the data outputs
are updated.
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may be
from capacitive or inductive coupling or coupling through
the ground plane. Even a tiny coupling factor can result in
discernible unwanted tones in the ADC output spectrum.
By randomizing the digital output before it is transmitted
off chip, these unwanted tones can be randomized, trading
a slight increase in the noise oor for a large reduction in
unwanted tone amplitude.
The digital output is “Randomized” by applying an exclu-
sive-OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT output
are not affected. The output Randomizer function is active
when the RAND pin is high.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2203/LTC2202 should drive a
minimum capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as a
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF. A resistor in
series with the output may be used but is not required
since the ADC has a series resistor of 43Ω on chip.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
The LTC2203/LTC2202 parallel digital output can be
selected for offset binary or 2’s complement format. The
format is selected with the MODE pin. This pin has a four
level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD.
An external resistor divider can be user to set the 1/3VDD
and 2/3VDD logic levels. Table 1 shows the logic states
for the MODE pin.
Table 1. MODE Pin Function
Clock Duty
MODE
Output Format
Cycle Stabilizer
0(GND)
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Overow Bit
An overow output bit (OF) indicates when the converter
is over-ranged or under-ranged. A logic high on the OF
pin indicates an overow or underow.
APPLICATIO S I FOR ATIO
W
U
相关PDF资料
PDF描述
LTC2202I#PBF 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2202I#TR 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2203C#PBF 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2203I 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
LTC2202C 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
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