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参数资料
| 型号： | LTC2205C |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封装： | 7 X7 MM, PLASTIC, MO-220, QFN-48 |
| 文件页数： | 13/28页 |
| 文件大小： | 804K |
| 代理商： | LTC2205C |
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LTC2205/LTC2204
20
22054p
CONVERTER OPERATION
The LTC2205/LTC2204 are CMOS pipelined multistep con-
verters with a front-end PGA. As shown in Figure 1, the con-
verter has ve pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2205/LTC2204 have two phases of operation, deter-
mined by the state of the differential ENC+/ENC– input pins.
For brevity, the text will refer to ENC+ greater than ENC– as
ENC high and ENC+ less than ENC– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage amplier. In
operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplied and
output by the residue amplier. Successive stages oper-
ate out of phase so that when odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplier which
drives the rst pipelined ADC stage. The rst stage acquires
the output of the S/H amplier during the high phase of
ENC. When ENC goes back low, the rst stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fth stage for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
APPLICATIO S I FOR ATIO
WU
U
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2205/
LTC2204 CMOS differential sample and hold. The differ-
ential analog inputs are sampled directly onto sampling
capacitors (CSAMPLE) through NMOS transitors. The
capacitors shown attached to each input (CPARASITIC) are
the summation of all other capacitance associated with
each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions for high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
Figure 2. Equivalent Input Circuit
CSAMPLE
4.9pF
VDD
LTC2005/LTC2004
AIN+
22054 F02
CSAMPLE
4.9pF
VDD
AIN–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
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| LTC2204C#PBF | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2205CUK | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2205CUK#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 65MSPS 48-QFN 制造商:Linear Technology 功能描述:ADC 16BIT 65MSPS 48QFN 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS QFN-48 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 65MSPS, QFN-48; Resolution (Bits):16bit; Sampling Rate:65MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:185mA; Digital IC Case Style:QFN; No. of Pins:48 ;RoHS Compliant: Yes |
| LTC2205CUK#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16-BIT 65MSPS 48-QFN |
| LTC2205CUK-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65Msps ADC |
| LTC2205CUK-14#PBF | 功能描述:IC ADC 14BIT 65MSPS 48-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
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