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参数资料
| 型号： | LTC2205C |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 |
| 封装： | 7 X7 MM, PLASTIC, MO-220, QFN-48 |
| 文件页数： | 16/28页 |
| 文件大小： | 804K |
| 代理商： | LTC2205C |
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LTC2205/LTC2204
23
22054p
ground for internal and external circuitry. This is also the
compensation capacitor for the reference; it will not be
stable without this capacitor. The minimum value required
for stability is 2.2F.
The internal programmable gain amplier provides the
internal reference voltage for the ADC. This amplier has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to VDD as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1F (or larger) ceramic capacitor.
Figure 7. A 2.25V Range ADC with
an External 2.5V Reference
VCM
SENSE
1.25V
3.3V
2.2
F
2.2
F
1
F
22054 F07
LTC2205/
LTC2204
LTC1461-2.5
2
6
4
APPLICATIO S I FOR ATIO
WU
U
differentially, primarily for noise immunity from common
mode noise sources. Each input is biased through a 6k
resistor to a 1.6V bias. The bias resistors set the DC oper-
ating point for transformer coupled drive circuits and can
set the logic threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
former coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a xed frequency sinusoidal
signal, lter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to VDD. Each input may be driven from ground to VDD for
single-ended drive.
PGA Pin
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25VP-P;
PGA = 1 selects an input range of 1.5VP-P. The 2.25V input
range has the best SNR; however, the distortion will be
higher for input frequencies above 100MHz. For applica-
tions with high input frequencies, the low input range will
have improved distortion; however, the SNR will be 1.8dB
worse. See the typical performance curves section.
Driving the Encode Inputs
The noise performance of the LTC2205/LTC2204 can
depend on the encode signal quality as much as for the
analog input. The encode inputs are intended to be driven
Figure 8. Transformer Driven Encode
VDD
LTC2205/LTC2204
22054 F08
VDD
ENC–
ENC+
1.6V
T1
1:4
0.1
F
ENCODE
INPUT
6k
TO INTERNAL
ADC CLOCK
DRIVERS
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| LTC2205CUK | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
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| LTC2205CUK#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16-BIT 65MSPS 48-QFN |
| LTC2205CUK-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 65Msps ADC |
| LTC2205CUK-14#PBF | 功能描述:IC ADC 14BIT 65MSPS 48-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
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