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参数资料
| 型号： | LTC2206IUK-14#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14-BIT 80MSPS 48-QFN |
| 标准包装： | 2,000 |
| 位数： | 14 |
| 采样率（每秒）： | 80M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 875mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN-EP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分 |
| 配用： | DC890B-ND - BOARD USB DATA COLLECTION |
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LTC2207-14/LTC2206-14
18
220714614fc
Figure 2. Equivalent Input Circuit
CSAMPLE
4.9pF
VDD
LTC2207-14/LTC2206-14
AIN+
2207614 F02
CSAMPLE
4.9pF
VDD
AIN–
ENC–
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1.8pF
CPARASITIC
1.8pF
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2207-14/
LTC2206-14 CMOS differential sample and hold. The dif-
ferential analog inputs are sampled directly onto sampling
capacitors (CSAMPLE) through NMOS transistors. The
capacitors shown attached to each input (CPARASITIC) are
the summation of all other capacitance associated with
each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions from high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specied performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The VCM output pin (Pin 2) is designed
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with a 2.2μF capacitor or greater.
Input Drive Impedance
As with all high performance, high speed ADCs the dy-
namic performance of the LTC2207-14/LTC2206-14 can
be inuenced by the input drive circuitry, particularly
the second and third harmonics. Source impedance and
input reactance can inuence SFDR. At the falling edge
of ENC the sample-and-hold circuit will connect the 4.9pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, hold-
ing the sampled input on the sampling capacitor. Ideally,
the input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recommended to have a
source impedance of 100
Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2206UK | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 105Msps/80Msps ADCs |
| LTC2206UK-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 105Msps/80Msps ADCs |
| LTC2207 | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 20Msps Low Power ADC |
| LTC2207-14 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 105Msps/80Msps ADCs |
| LTC2207CUK | 制造商:Linear Technology 功能描述:ADC Single Pipelined 105Msps 16-bit Parallel 48-Pin QFN EP |
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