参数资料
型号: LTC2232IUK#TR
厂商: Linear Technology
文件页数: 7/28页
文件大小: 0K
描述: IC ADC 10BIT 105MSPS SAMPL 48QFN
标准包装: 2,000
位数: 10
采样率(每秒): 105M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 535mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-QFN-EP(7x7)
包装: 带卷 (TR)
输入数目和类型: 1 个单端,双极; 1 个差分,双极
LTC2232/LTC2233
15
22323fa
APPLICATIO S I FOR ATIO
WU
U
CONVERTER OPERATION
As shown in Figure 1, the LTC2232/LTC2233 is a CMOS
pipelined multistep converter. The converter has five
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive applica-
tions, the analog inputs can be driven single-ended with
slightly worse harmonic distortion. The encode input is
differential for improved common mode noise immunity.
The LTC2232/LTC2233 has two phases of operation,
determined by the state of the differential ENC+/ENCinput
pins. For brevity, the text will refer to ENC+ greater than
ENCas ENC high and ENC+ less than ENCas ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2232/
LTC2233 CMOS differential sample-and-hold. The analog
inputs are connected to the sampling capacitors (CSAMPLE)
through NMOS transistors. The capacitors shown at-
tached to each input (CPARASITIC) are the summation of all
other capacitance associated with each input.
Figure 2. Equivalent Input Circuit
CSAMPLE
1.6pF
VDD
LTC2232/LTC2233
AIN
+
22323 F02
CSAMPLE
1.6pF
VDD
AIN
ENC
ENC+
1.6V
6k
1.6V
6k
CPARASITIC
1pF
CPARASITIC
1pF
15
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LTC2233CUK#TR 功能描述:IC ADC 10BIT 80MSPS SAMPL 48QFN RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率(每秒):45k 数据接口:串行 转换器数目:2 功率耗散(最大):315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC(0.295",7.50mm 宽) 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端,单极