参数资料
| 型号： | LTC2240IUP-10#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 170MSPS 64-QFN |
| 标准包装： | 40 |
| 位数： | 10 |
| 采样率（每秒）： | 170M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 638mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-WFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，双极 |
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LTC2240-10
16
224010fb
APPLICATIONS INFORMATION
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTC2240-10 can be inuenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can inuence SFDR. At the falling edge of ENC, the
sample-and-hold circuit will connect the 2pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge the
sampling capacitor during the sampling period 1/(2fS);
however, this is not always possible and the incomplete
settling may degrade the SFDR. The sampling glitch has
been designed to be as linear as possible to minimize the
effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2240-10 being driven by an RF
transformer with a center tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100Ω for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
Figure 5 shows a capacitively-coupled input circuit. The im-
pedance seen by the analog inputs should be matched.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
Figure 4. Differential Drive with an Amplier
Figure 5. Capacitively-Coupled Drive
25Ω
10Ω
0.1μF
AIN
+
AIN
+
AIN
–
AIN
–
12pF
2.2μF
VCM
LTC2240-10
ANALOG
INPUT
0.1μFT1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
224010 F03
25Ω
50Ω
AIN
+
AIN
+
AIN
–
AIN
–
12pF
2.2μF
3pF
VCM
LTC2240-10
224010 F04
–
+
CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
3pF
0.1μF
25Ω
0.1μF
VCM
AIN
+
AIN
+
AIN
–
AIN
–
100Ω
ANALOG
INPUT
12pF
224010 F05
2.2μF
0.1μF
25Ω
LTC2240-10
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2240IUP-10-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:10-Bit, 170Msps ADC |
| LTC2240IUP-10-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:10-Bit, 170Msps ADC |
| LTC2240IUP-12 | 制造商:Linear Technology 功能描述:ADC Single Pipelined 170Msps 12-bit Parallel/LVDS 64-Pin QFN EP |
| LTC2240IUP-12#PBF | 功能描述:IC ADC 12BIT 170MSPS 64-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| LTC2240IUP-12#TR | 制造商:Linear Technology 功能描述:ADC Single Pipelined 170Msps 12-bit Parallel/LVDS 64-Pin QFN EP T/R |
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