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参数资料
| 型号： | LTC2246HLU#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封装： | 5 X 5 MM, LEAD FREE, PLASTIC, MS-026, TQFP-32 |
| 文件页数： | 14/16页 |
| 文件大小： | 273K |
| 代理商： | LTC2246HLU#PBF |
LTC2246H
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PIN FUNCTIONS
AIN+ (Pin 1): Positive Differential Analog Input.
AIN- (Pin 2): Negative Differential Analog Input.
GND (Pins 3, 6, 8): ADC Power Ground.
REFH (Pin 4): ADC High Reference. Bypass to pin 5 with
a 0.1μF ceramic chip capacitor as close to the pin as
possible. Also bypass to pin 5 with an additional 2.2μF
ceramic chip capacitor and to ground with a 1μF ceramic
chip capacitor.
REFL (Pin 5): ADC Low Reference. Bypass to pin 4 with
a 0.1μF ceramic chip capacitor as close to the pin as
possible. Also bypass to pin 4 with an additional 2.2μF
ceramic chip capacitor and to ground with a 1μF ceramic
chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1μF
ceramic chip capacitors.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting
SHDN to GND and OE to GND results in normal operation
with the outputs enabled. Connecting SHDN to GND and
OE to VDD results in normal operation with the outputs at
high impedance. Connecting SHDN to VDD and OE to GND
results in nap mode with the outputs at high impedance.
Connecting SHDN to VDD and OE to VDD results in sleep
mode with the outputs at high impedance.
If the clock duty cycle stabilizer is used, a >1μs high pulse
should be applied to the SHDN pin once the power supplies
are stable at power up.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin func-
tion.
D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23,
24, 25, 26, 27): Digital Outputs. D13 is the MSB.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1μF ceramic chip capacitor.
OF (Pin 28): Over/Under Flow Output. High when an over
or under ow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2μF ceramic chip capacitor.
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2246HLU#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246HLU#TR | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246HLU | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246IUH | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32 |
| LTC2246IUH#TR | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2246HLX | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 25Msps 125°C ADC In LQFP |
| LTC2246HLX#PBF | 功能描述:IC ADC 14BIT 25MSPS 48-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2246HLX-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 25Msps 125°C ADC In LQFP |
| LTC2246HLX-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 25Msps 125°C ADC In LQFP |
| LTC2246HLX-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 25Msps 125°C ADC In LQFP |
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