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参数资料
| 型号： | LTC2246HLU#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| 封装： | 5 X 5 MM, LEAD FREE, PLASTIC, MS-026, TQFP-32 |
| 文件页数： | 2/16页 |
| 文件大小： | 273K |
| 代理商： | LTC2246HLU#PBF |
LTC2246H
10
2246hf
APPLICATIONS INFORMATION
output by the residue amplier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplier which drives the rst pipelined ADC
stage. The rst stage acquires the output of the S/H dur-
ing this high phase of CLK. When CLK goes back low, the
rst stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
third stage. An identical process is repeated for the third,
fourth and fth stages, resulting in a fth stage residue
that is sent to the sixth stage ADC for nal evaluation.
Each ADC stage following the rst has additional range to
accommodate ash and amplier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2246H
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (CSAMPLE) through
NMOS transistors. The capacitors shown attached to
each input (CPARASITIC) are the summation of all other
capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage. When
CLK transitions from low to high, the sampled input voltage
is held on the sampling capacitors. During the hold phase
when CLK is high, the sampling capacitors are disconnected
from the input and the held voltage is passed to the ADC
core for processing. As CLK transitions from high to low,
VDD
15
Ω
15
Ω
CPARASITIC
1pF
CPARASITIC
1pF
CSAMPLE
4pF
CSAMPLE
4pF
LTC2246H
AIN+
AIN–
CLK
2246 F02
Figure 2. Equivalent Input Circuit
the inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional
to the change in voltage between samples will be seen
at this time. If the change between the last sample and
the new sample is small, the charging glitch seen at the
input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should
be connected to VCM or a low noise reference voltage
between 1V and 1.5V.
Common Mode Bias
For optimal performance the analog inputs should be driven
differentially. Each input should swing ±0.5V for the 2V
range or ±0.25V for the 1V range, around a common mode
voltage of 1.5V. The VCM output pin (Pin 31) may be used
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with a 2.2μF or greater capacitor.
相关PDF资料 |
PDF描述 |
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| LTC2246HLU#TRPBF | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246HLU#TR | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246HLU | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32 |
| LTC2246IUH | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32 |
| LTC2246IUH#TR | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2246HLX | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 25Msps 125°C ADC In LQFP |
| LTC2246HLX#PBF | 功能描述:IC ADC 14BIT 25MSPS 48-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2246HLX-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 25Msps 125°C ADC In LQFP |
| LTC2246HLX-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 25Msps 125°C ADC In LQFP |
| LTC2246HLX-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 25Msps 125°C ADC In LQFP |
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