参数资料
型号: LTC2262CUJ-14#TRPBF
厂商: Linear Technology
文件页数: 13/28页
文件大小: 0K
描述: IC ADC 14BIT 150MSPS 40-QFN
标准包装: 2,000
位数: 14
采样率(每秒): 150M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 171mW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 带卷 (TR)
输入数目和类型: 1 个差分
配用: DC890B-ND - BOARD USB DATA COLLECTION
LTC2262-14
20
226214fc
For more information www.linear.com/LTC2262-14
switching of most of the bits will cause large currents in
the ground plane. By inverting every other bit, the alter-
nate bit polarity mode makes half of the bits transition
high while half of the bits transition low. To first order,
this cancels current flow in the ground plane, reducing
the digital noise.
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output ran-
domizer—either, both or neither function can be on at the
sametime.Whenalternatebitpolaritymodeison,thedata
format is offset binary and the 2’s complement control bit
has no effect. The alternate bit polarity mode is enabled
by serially programming mode control register A4.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13-D0) to known values:
All 1s: All outputs are 1
All 0s: All outputs are 0
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Checkerboard:Outputschangefrom101010101010101
to 010101010101010 on alternating samples
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate-bit-polarity.
Output Disable
The digital outputs may be disabled by serially program-
mingmodecontrolregisterA3.Alldigitaloutputsincluding
OFandCLKOUTaredisabled.Thehighimpedancedisabled
state is intended for long periods of inactivity—it is too
slow to multiplex a data bus between multiple converters
at full speed.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire A/D converter is powered
down,resultingin0.5mWpowerconsumption.Sleepmode
is enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on VREF,
REFH, and REFL. For the suggested values in Figure 8,
the A/D will stabilize after 2ms.
In nap mode the A/D core is powered down while the
internal reference circuits stay active, allowing faster
wake-up than from sleep mode. Recovering from nap
APPLICATIONS INFORMATION
CLKOUT
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0
226214 F15
OF
D13
D12
D2
D1
D0
RANDOMIZER
ON
D13
FPGA
PC BOARD
D12
D2
D1
D0
226214 F16
D0
D1/D0
D2/D0
D12/D0
D13/D0
OF
CLKOUT
LTC2262-14
Figure 15. Functional Equivalent of Digital Output Randomizer
Figure 16. Unrandomizing a Randomized Digital
Output Signal
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