参数资料
型号: LTC2266CUJ-14#PBF
厂商: Linear Technology
文件页数: 29/32页
文件大小: 0K
描述: IC ADC 14BIT SER 80MSPS 40-QFN
标准包装: 61
位数: 14
采样率(每秒): 80M
数据接口: Serial LVDS
转换器数目: 2
功率耗散(最大): 257mW
电压电源: 单电源
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-QFN(6x6)
包装: 管件
输入数目和类型: 2 Differential; 2 Single-Ended
配用: DC1371A-ND - BOARD USB DATA ACQUISITION HS
LTC2268-14/
LTC2267-14/LTC2266-14
6
22687614fa
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD,
they will be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above
VDD they will not be clamped by internal diodes. This product can handle
input currents of greater than 100mA below GND without latchup.
Note 5: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2268), 105MHz
(LTC2267), or 80MHz (LTC2266), 2-lane output mode, differential ENC+/
ENC= 2VP-P sine wave, input range = 2VP-P with differential drive, unless
otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL DATA OUTPUTS (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1/(8 fS)
1/(7 fS)
1/(6 fS)
1/(16 fS)
1/(14 fS)
1/(12 fS)
s
tFRAME
FR to DCO Delay
(Note 8)
l
0.35 tSER
0.5 tSER
0.65 tSER
s
tDATA
DATA to DCO Delay
(Note 8)
l
0.35 tSER
0.5 tSER
0.65 tSER
s
tPD
Propagation Delay
(Note 8)
l
0.7n + 2 tSER 1.1n + 2 tSER 1.5n + 2 tSER
s
tR
Output Rise Time
Data, DCO, FR, 20% to 80%
0.17
ns
tF
Output Fall Time
Data, DCO, FR, 20% to 80%
0.17
ns
DCO Cycle-Cycle Jitter
tSER = 1ns
60
psP-P
Pipeline Latency
6
Cycles
SPI PORT TIMING (Note 8)
tSCK
SCK Period
Write Mode
Readback Mode, CSDO = 20pF, RPULLUP = 2k
l
40
250
ns
tS
CS to SCK Setup Time
l
5
ns
tH
SCK to CS Setup Time
l
5
ns
tDS
SDI Setup Time
l
5
ns
tDH
SDI Hold Time
l
5
ns
tDO
SCK falling to SDO Valid
Readback Mode, CSDO = 20pF, RPULLUP = 2k l
125
ns
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 8: Guaranteed by design, not subject to test.
Note 9: VDD = OVDD = 1.8V, fSAMPLE = 125MHz (LTC2268), 105MHz
(LTC2267), or 80MHz (LTC2266), 2-lane output mode, ENC+ = single-
ended 1.8V square wave, ENC= 0V, input range = 2VP-P with differential
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
Note 10: Recommended operating conditions.
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
data rate is 1000Mbps so tSER must be greater than or equal to 1ns.
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