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参数资料
| 型号： | LTC2272CUJ#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| 封装： | 6 X 6 MM, PLASTIC, QFN-40 |
| 文件页数： | 13/44页 |
| 文件大小： | 767K |
| 代理商： | LTC2272CUJ#TR |
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LTC2273/LTC2272
20
22732fa
DEFINITIONS
a D16.2 will be transmitted after the comma, otherwise
a D5.6 will be transmitted. The result is that the ending
disparity of an idle ordered set will always be negative.
Initial Frame Synchronization
The process of communicating frame synchroniza-tion
information to the receiver upon the request of the receiver.
For JESD204 compliance, K28.5 commas are transmitted
as the preamble. Once the preamble has been detected
the receiver terminates the synchronization request, and
the preamble transmission continues until the end of the
frame. The receiver designates the rst normal data word
after the preamble to be the start of the data frame.
Octet
The 8-bit input to an 8B/10B encoder, or the 8-bit output
from an 8B/10B decoder.
Run-Length Limited (RLL)
The result of limiting the number of consecutive 1’s or
0’s in a data stream by encoding the data prior to serial
transmission.
This process guarantees that there will be an adequate
number of transitions in the serial data for the receiver
to lock onto with a phase-locked loop and recover the
high-speed clock.
Running Disparity
In order to maintain DC balance there are two possible
8B/10B output code-groups for each input octet. The
running disparity is calculated to determine which of the
two code-groups should be transmitted to maintain DC
balance.
The disparity of a code-group is analyzed in two segments
called sub-blocks. Sub-block1 consists of the rst six bits
of a code-group and sub-block2 consists of the last four
bits of a code-group. When a sub-block is more heavily
weighted with 1’s the running disparity is positive, and when
it is more heavily weighted with 0’s the running disparity
is negative. When the number of 1’s and 0’s are equal in a
sub-block, the running disparity remains unchanged.
The polarity of the current running disparity determines
which code-group should be transmitted to maintain DC
balance. For a complete description of disparity rules, refer
to IEEE Std 802.3-2002 part3, Clause 36.2.4.4.
Pseudo Random Bit Sequence (PRBS)
A data sequence having a random nature over a nite
interval. The most commonly used PRBS test patterns
may be described by a polynomial in the form of 1 + xm +
xn and have a random nature for the length of up to 2n – 1
bits, where n indicates the order of the PRBS polynomial
and m plays a role in maximizing the length of the random
sequence.
Scrambler
A logic block that applies a pseudo random bit sequence
to the input octets to minimize the tonal content of the
high-speed serial bit stream.
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2272IUJ | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2273CUJ#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2272CUJ | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2273CUJ | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2272IUJ#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2272CUJ-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Serial Output ADC |
| LTC2272IUJ | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Serial Output ADC |
| LTC2272IUJ#PBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 40-QFN |
| LTC2272IUJ#TRPBF | 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 40-QFN |
| LTC2272IUJ-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Serial Output ADC |
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