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参数资料
| 型号： | LTC2272CUJ |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| 封装： | 6 X 6 MM, PLASTIC, QFN-40 |
| 文件页数： | 19/44页 |
| 文件大小： | 767K |
| 代理商： | LTC2272CUJ |
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LTC2273/LTC2272
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APPLICATIONS INFORMATION
Driving the Encode Inputs
The noise performance of the LTC2273/LTC2272 can
depend on the encode signal quality as much as for the
analog input. The encode inputs are intended to be driven
differentially, primarily for noise immunity from common
mode noise sources. Each input is biased through a 6k
resistor to a 1.6V bias. The bias resistors set the DC oper-
ating point for transformer coupled drive circuits and can
set the logic threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
former coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a xed frequency sinusoidal
signal, lter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.4V
to 3V. Each input may be driven from ground to VDD for
single-ended drive.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2273 is
80Msps. The maximum conversion rate for the LTC2272
is 65Msps.
The lower limit of the LTC2273/LTC2272 sample rate is
determined by the PLL minimum operating frequency of
20Msps.
For the ADC to operate properly, the internal CLK signal
should have a 50% duty cycle. A duty cycle stabilizer cir-
cuit has been implemented on chip to facilitate non-50%
ENC duty cycles.
Data Format
The MSBINV pin selects the ADC data format. A low level
selects offset binary format (code 0 corresponds to –FS, and
code 65535 corresponds to +FS). A high level on MSBINV
selects 2’s complement format (code –32768 corresponds
to –FS and code 32767 corresponds to +FS.
Shutdown Modes
The assertion of both SHDN pins will shut down the ADC
and the serial interface and place the chip in a low-cur-
rent mode.
Internal Dither
The LTC2273/LTC2272 are 16-bit ADC with a very linear
transfer function; however, at low input levels even slight
imperfections in the transfer function will result in unwanted
tones. Small errors in the transfer function are usually a
result of ADC element mismatches. An optional internal
dither mode can be enabled to randomize the input location
on the ADC transfer curve, resulting in improved SFDR
for low signal levels.
As shown in Figure 11, the output of the sample-and-hold
amplier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted digitally from the ADC result. If the
dither DAC is precisely calibrated to the ADC, very little
of the dither signal will be seen at the output. The dither
signal that does leak through will appear as white noise.
The dither DAC is calibrated to result in less than 0.5dB
elevation in the noise oor of the ADC, as compared to
the noise oor with dither off.
相关PDF资料 |
PDF描述 |
|---|---|
| LTC2273CUJ | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2272IUJ#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2273IUJ#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2273IUJ | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| LTC2274CUJ#TR | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2272CUJ#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Serial 40-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 40-QFN 制造商:Linear Technology 功能描述:A/D Converter IC 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 65MSPS, QFN-40; Resolution (Bits):16bit; Sampling Rate:65MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:300mA; Digital IC Case Style:QFN; No. of Pins:40 ;RoHS Compliant: Yes |
| LTC2272CUJ#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Serial 40-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS 40-QFN |
| LTC2272CUJ-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Serial Output ADC |
| LTC2272CUJ-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Serial Output ADC |
| LTC2272CUJ-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:16-Bit, 80Msps/65Msps Serial Output ADC |
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