- 您现在的位置：买卖IC网 > PDF目录10212 > LTC2280CUP#TRPBF (Linear Technology)IC ADC DUAL 10BIT 105MSPS 64-QFN PDF资料下载
参数资料
| 型号： | LTC2280CUP#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 10BIT 105MSPS 64-QFN |
| 标准包装： | 2,000 |
| 位数： | 10 |
| 采样率（每秒）： | 105M |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 630mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-WFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，双极; 2 个差分, 双极 |
LTC2280
18
2280fa
APPLICATIO S I FOR ATIO
WU
U
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
Table 2. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stabilizer
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA, and
Channel B is controlled by SHDNB and OEB. The nap, sleep
and output enable modes of the two channels are completely
independent, so it is possible to have one channel operat-
ing while the other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2280 can be multiplexed onto
a single data bus if the sample rate is 80Msps or less. The
MUX pin is a digital input that swaps the two data busses.
If MUX is High, Channel A comes out on DA0-DA9, OFA;
Channel B comes out on DB0-DB9, OFB. If MUX is Low, the
output busses are swapped and Channel A comes out on
DB0-DB9, OFB; Channel B comes out on DA0-DA9, OFA.
To multiplex both channels onto a single output bus, con-
nect MUX, CLKA and CLKB together (see the Timing Dia-
gram for the multiplexed mode). The multiplexed data is
available on either data bus—the unused data bus can be
disabled with its OE pin.
Grounding and Bypassing
The LTC2280 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an inter-
nal ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-
tors must be located as close to the pins as possible. Of
particular importance is the 0.1
F capacitor between
REFH and REFL. This capacitor should be placed as close
to the device as possible (1.5mm or less). A size 0402
相关PDF资料 |
PDF描述 |
|---|---|
| SP3084EEN-L/TR | IC TXRX RS485/RS422 ESD 8NSOIC |
| AD7357BRUZ-RL | IC ADC 14BITDUAL 4.MSPS 16TSSOP |
| SP3083EEN-L/TR | IC TXRX RS485/RS422 ESD 14NSOIC |
| SP3081EEN-L/TR | IC TXRX RS485/RS422 ESD 8NSOIC |
| SP3080EEN-L/TR | IC TXRX RS485/RS422 ESD 14NSOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2280IUP | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 10-Bit, 105Msps Low Noise 3V ADC |
| LTC2280IUP#PBF | 功能描述:IC ADC DUAL 10BIT 105MSPS 64-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| LTC2280IUP#TRPBF | 功能描述:IC ADC DUAL 10BIT 105MSPS 64-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| LTC2280UP | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 10-Bit, 105Msps Low Noise 3V ADC |
| LTC2281 | 制造商:LINER 制造商全称:Linear Technology 功能描述:Dual 10-Bit, 125Msps Low Power 3V ADC |
发布紧急采购，3分钟左右您将得到回复。