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参数资料
| 型号： | LTC2351CUH-12 |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 6-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC32 |
| 封装： | 5 X 5 MM, PLASTIC, MO-220WHHD, QFN-32 |
| 文件页数： | 10/20页 |
| 文件大小： | 273K |
| 代理商： | LTC2351CUH-12 |
18
LTC2351-12
235112f
APPLICATIO S I FOR ATIO
WU
UU
High quality tantalum and ceramic bypass capacitors should
be used at the VCC, VDD and VREF pins as shown in the
Block Diagram on the first page of this data sheet. For
optimum performance, a 10
F surface mount tantalum
capacitor with a 0.1
F ceramic is recommended for the
VCC, VDD and VREF pins. Alternatively, 10F ceramic chip
capacitors such as X5R or X7R may be used. The capaci-
tors must be located as close to the pins as possible. The
traces connecting the pins and the bypass capacitors must
be kept short and should be made as wide as possible. The
VCC and VDD bypass capacitor returns to the ground plane
and the VREF bypass capacitor returns to the Pin 22. Care
should be taken to place the 0.1
F VCC and VDD bypass
capacitor as close to Pins 24 and 25 as possible.
Figure 6 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC2351-12 Exposed Pad. The ground return from the
LTC2351-12 to the power supply should be low imped-
ance for noise-free operation. The Exposed Pad of the 32-
pin QFN package is also internally tied to the ground pads.
The Exposed Pad should be soldered on the PC board to
reduce ground connection inductance. All ground pins
(GND, DGND, OGND) must be connected directly to the
same ground plane under the LTC2351-12.
HARDWARE INTERFACE TO TMS320C54x
The LTC2351-12 is a serial output ADC whose interface
has been designed for high speed buffered serial ports in
fast digital signal processors (DSPs). Figure 7 shows an
example of this interface using a TMS320C54X.
The buffered serial port in the TMS320C54x has direct
access to a 2kB segment of memory. The ADC’s serial
data can be collected in two alternating 1kB segments, in
real time, at the full 1.5Msps conversion rate of the
LTC2351-12. The DSP assembly code sets frame sync
mode at the BFSR pin to accept an external positive going
pulse and the serial clock at the BCLKR pin to accept an
external positive edge clock. Buffers near the LTC2351-12
may be added to drive long tracks to the DSP to prevent
corruption of the signal to LTC2351-12. This configura-
tion is adequate to traverse a typical system board, but
source resistors at the buffer outputs and termination
resistors at the DSP, may be needed to match the charac-
teristic impedance of very long transmission lines. If you
need to terminate the SDO transmission line, buffer it first
with one or two 74ACxx gates. The TTL threshold inputs of
the DSP port respond properly to the 3V swing used with
the LTC2351-12.
Figure 6. Recommended Layout
VDD BYPASS,
0.1
F, 0402
OVDD BYPASS,
0.1
F, 0402
VREF BYPASS,
10
F, 0805
VCC BYPASS,
0.1
F, 0402 AND
10
F, 0805
235112 F06
3
30
32
1
2
3-WIRE SERIAL
INTERFACE LINK
OVDD
CONV
SCK
LTC2351-12
SDO
VCC
BFSR
BCLKR
TMS320C54x
BDR
OGND
31
DGND
CONV
0V TO 3V LOGIC SWING
CLK
5V
3V
B11
B10
Figure 7. DSP Serial Interface to TMS320C54x
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