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参数资料
| 型号： | LTC2356IMSE-12#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 |
| 封装： | PLASTIC, MSOP-10 |
| 文件页数： | 15/16页 |
| 文件大小： | 266K |
| 代理商： | LTC2356IMSE-12#TR |
8
LTC2356-12/LTC2356-14
2356f
AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates
fully differentially with respect to AIN– with a –1.25V to
1.25V differential swing with respect to AIN– and a 0V to
VDD common mode swing.
AIN– (Pin 2): Inverting Analog Input. AIN– operates fully
differentially with respect to AIN+ with a 1.25V to –1.25V
differential swing with respect to AIN+ and a 0V to VDD
common mode swing.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND and
to a solid analog ground plane with a 10
F ceramic
capacitor (or 10
F tantalum in parallel with 0.1F ce-
ramic). Can be overdriven by an external reference be-
tween 2.55V and VDD.
GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
VDD (Pin 7): 3.3V Positive Supply. This single power pin
supplies 3.3V to the entire device. Bypass to GND and to
a solid analog ground plane with a 10
F ceramic capacitor
(or 10
F tantalum in parallel with 0.1F ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1
F bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each set of
output data words represents the difference between
AIN+ and AIN– analog inputs at the start of the previous
conversion. The output format is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. Responds to TTL (
≤3.3V) and 3.3V CMOS levels.
One or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the analog input
signal and starts the conversion on the rising edge.
Responds to TTL (
≤3.3V) and 3.3V CMOS levels. Two
CONV pulses with SCK in fixed high or fixed low state start
Nap mode. Four or more CONV pulses with SCK in fixed
high or fixed low state start Sleep mode.
UU
U
PI FU CTIO S
BLOCK DIAGRA
W
2356 BD
–
+
1
2
7
3
4
S & H
GND
EXPOSED PAD
LTC2356-14
VREF
10
F
AIN
–
AIN
+
14-BIT ADC
3.3V
10
F
14
14-BIT
LATCH
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
2.5V
REFERENCE
TIMING
LOGIC
VDD
SDO
CONV
SCK
5
6
11
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