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参数资料
| 型号： | LTC2356IMSE-12#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10 |
| 封装： | PLASTIC, MSOP-10 |
| 文件页数： | 5/16页 |
| 文件大小： | 266K |
| 代理商： | LTC2356IMSE-12#TR |
13
LTC2356-12/LTC2356-14
2356f
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2356-12/LTC2356-14, a printed
circuit board with ground plane is required. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the two input
wires should be kept matched.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in the
Block Diagram on the first page of this data sheet. For
optimum performance, a 10
F surface mount Tantalum
capacitor with a 0.1
F ceramic is recommended for the
VDD and VREF pins. Alternatively, 10F ceramic chip
capacitors such as Murata GRM219R60J106M may
be used. The capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Figure 7 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC2356-12/LTC2356-14 GND (Pins 4, 5, 6 and
exposed pad). The ground return from the LTC2356-12/
LTC2356-14 (Pins 4, 5, 6 and exposed pad) to the power
supply should be low impedance for noise free operation.
In applications where the ADC data outputs and control
signals are connected to a continuously active micropro-
cessor bus, it is possible to get errors in the conversion
results. These errors are due to feedthrough from the
microprocessor to the successive approximation com-
parator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.
POWER-DOWN MODES
Upon power-up, the LTC2356-12/LTC2356-14 is initial-
ized to the active state and is ready for conversion. The Nap
and Sleep mode waveforms show the power-down modes
for the LTC2356-12/LTC2356-14. The SCK and CONV
inputs control the power-down modes (see Timing
Diagrams). Two rising edges at CONV, without any
intervening rising edges at SCK, put the LTC2356-12/
LTC2356-14 in Nap mode and the power consumption
drops from 18mW to 4mW. The internal reference
remains powered in Nap mode. One or more rising edges
at SCK wake up the LTC2356-12/LTC2356-14 very quickly,
and CONV can start an accurate conversion within a clock
cycle. Four rising edges at CONV, without any intervening
rising edges at SCK, put the LTC2356-12/LTC2356-14 in
Sleep mode and the power consumption drops from
18mW to 13
W. One or more rising edges at SCK wake up
the LTC2356-12/LTC2356-14 for operation. The internal
reference (VREF ) takes 2ms to slew and settle with a 10F
load. Note that, using sleep mode more frequently than
every 2ms, compromises the settled accuracy of the
APPLICATIO S I FOR ATIO
WU
U
Figure 7. Recommended Layout
2356 F07
FREQUENCY (Hz)
MAGNITUDE
(dB)
–60
–30
–20
2356 F06b
–70
–80
–120
–100
0
–10
–40
–50
–90
–110
0
371k
185k
556k
741k
Figure 6b. LTC2356-12 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
VREF BYPASS 0805 SIZE
VDD BYPASS 0805 SIZE
OPTIONAL INPUT FILTERING
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