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参数资料
| 型号： | LTC2364IMS-18#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 20/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT 250K 1CH 16MSOP |
| 产品培训模块： | LTC2369- 18-/16-bit Pseudo-Differential SAR ADC Family Overview |
| 标准包装： | 37 |
| 位数： | 18 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 4.25mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TFSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 16-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | DC1813A-H-ND - BOARD SAR ADC LTC2364-18 |
LTC2364-18
5
236418f
ADC TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REFor
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 250kHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Zero-scale error is the offset voltage measured from 0.5LSB
when the output code flickers between 00 0000 0000 0000 0000 and
00 0000 0000 0000 0001. Full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale 5V input with a
5V reference voltage.
Note 9: fSMPL = 250kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
Figure 1. Voltage Levels for Timing Specifications
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSCK
SCK Period
(Notes 11, 12)
l
10
ns
tSCKH
SCK High Time
l
4
ns
tSCKL
SCK Low Time
l
4
ns
tSSDISCK
SDI Setup Time From SCK
↑
(Note 11)
l
4
ns
tHSDISCK
SDI Hold Time From SCK
↑
(Note 11)
l
1
ns
tSCKCH
SCK Period in Chain Mode
tSCKCH = tSSDISCK + tDSDO (Note 11)
l
13.5
ns
tDSDO
SDO Data Valid Delay from SCK
↑
CL = 20pF (Note 11)
l
9.5
ns
tHSDO
SDO Data Remains Valid Delay from SCK
↑
CL = 20pF (Note 10)
l
1
ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
CL = 20pF (Note 10)
l
5
ns
tEN
Bus Enable Time After RDL
↓
(Note 11)
l
16
ns
tDIS
Bus Relinquish Time After RDL
↑
(Note 11)
l
13
ns
0.8*OVDD
0.2*OVDD
50%
236418 F01
0.2*OVDD
0.8*OVDD
0.2*OVDD
0.8*OVDD
tDELAY
tWIDTH
tDELAY
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