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参数资料
| 型号： | LTC2364IMS-18#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT 250K 1CH 16MSOP |
| 产品培训模块： | LTC2369- 18-/16-bit Pseudo-Differential SAR ADC Family Overview |
| 标准包装： | 37 |
| 位数： | 18 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 4.25mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TFSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 16-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | DC1813A-H-ND - BOARD SAR ADC LTC2364-18 |
LTC2364-18
14
236418f
APPLICATIONS INFORMATION
Power Supply Sequencing
The LTC2364-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2364-18
has a power-on-reset (POR) circuit that will reset the
LTC2364-18 at initial power-up or whenever the power
supply voltage drops below 1V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 20s after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
TIMING AND CONTROL
CNV Timing
The LTC2364-18 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up the
LTC2364-18.Onceaconversionhasbeeninitiated,itcannot
berestarteduntiltheconversioniscomplete.Foroptimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2364-18 powers down and begins acquiring the
input signal.
Acquisition
AproprietarysamplingarchitectureallowstheLTC2364-18
to begin acquiring the input signal for the next conver-
sion 527ns after the start of the current conversion. This
extends the acquisition time to 3.460s, easing settling
requirements and allowing the use of extremely low power
ADC drivers. (Refer to the Timing Diagram.)
Internal Conversion Clock
The LTC2364-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 3s.
Auto Power-Down
The LTC2364-18 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of CNV.
During power down, data from the last conversion can
be clocked out. To minimize power dissipation during
power down, disable SDO and turn off SCK. The auto
power-down feature will reduce the power dissipation of
the LTC2364-18 as the sampling frequency is reduced.
Since power is consumed only during a conversion, the
LTC2364-18remainspowereddownforalargerfractionof
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 9.
DIGITAL INTERFACE
The LTC2364-18 has a serial digital interface. The flexible
OVDD supply allows the LTC2364-18 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
anexternalclockisappliedtotheSCKpinifSDOisenabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
20MHz, a 250ksps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D17 remains valid till the first rising edge of SCK.
Figure 9. Power Supply Current of the LTC2364-18
Versus Sampling Rate
SAMPLING RATE (kHz)
1
0
POWER
SUPPLY
CURRENT
(mA)
0.2
0.4
0.6
0.8
1.2
1.6
1.0
1.4
50
100
150
200
IVDD
236418 F09
250
IOVDD
IREF
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