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| 型号： | LTC2440IGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC DIFFER 24-BIT HS 16-SSOP |
| 标准包装： | 100 |
| 位数： | 24 |
| 采样率（每秒）： | 3.5k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 40mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，双极 |
| 产品目录页面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC570A-ND - BOARD DELTA SIGMA ADC LTC2440 |
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LTC2440
17
2440fd
APPLICATIONS INFORMATION
Figure 8. Internal Serial Clock, Single Cycle Operation
controller indicating the conversion result is ready. EOC
= 1 (BUSY = 1) while the conversion is in progress and
EOC = 0 (BUSY = 0) once the conversion enters the low
power sleep state. On the falling edge of EOC/BUSY, the
conversion result is loaded into an internal static shift
register. The device remains in the sleep state until the
rst rising edge of SCK. Data is shifted out the SDO pin
on each falling edge of SCK enabling external circuitry to
latch data on the rising edge of SCK. EOC can be latched
on the rst rising edge of SCK. On the 32nd falling edge
of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a
new conversion has begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode,
the EXT pin must be tied HIGH.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alterna-
tively, BUSY (Pin 15) may be used to monitor the status
of the conversion in progress. BUSY is HIGH during the
conversion and goes LOW at the conclusion. It remains
LOW until the result is read from the device.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit the sleep state and enter the data
output state if CS remains LOW. In order to prevent the
device from exiting the low power sleep state, CS must
be pulled HIGH before the rst rising edge of SCK. In the
internal SCK timing mode, SCK goes HIGH and the device
begins outputting data at time tEOCtest after the falling edge
of CS (if EOC = 0) or tEOCtest after EOC goes LOW (if CS is
LOW during the falling edge of EOC). The value of tEOCtest
is 500ns. If CS is pulled HIGH before time tEOCtest, the
device remains in the sleep state. The conversion result
is held in the internal static shift register.
If CS remains LOW longer than tEOCtest, the rst rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
SDO
BUSY
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB24
BIT 5
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2440 F08
<tEOCtest
Hi-Z
TEST EOC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
REF+
REF–
SCK
BUSY
IN+
IN–
SDO
GND
CS
EXT
2
14
3
4
13
5
6
12
1, 8, 9, 16
11
10
VCC
15
SDI
7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
3-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
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