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参数资料
| 型号： | LTC2446IUHF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 25/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 8CH HI SPEED 38QFN |
| 标准包装： | 52 |
| 位数： | 24 |
| 采样率（每秒）： | 8k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 40mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 管件 |
| 输入数目和类型： | 8 个单端，双极；4 个差分，双极 |
| 产品目录页面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC847A-ND - BOARD DELTA SIGMA ADC LTC2446 |
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LTC2446/LTC2447
6
24467fa
contains an enable bit which determines if a new channel/
speed is selected. If this bit is low the following conversion
remains at the same speed and selected channel. The
serial data input is applied to the device under control of
the serial clock (SCK) during the data output cycle. The
first conversion following a new channel/speed is valid.
FO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock. When FO is con-
nected to VCC or GND, the converter uses its internal
oscillator running at 9MHz. The conversion rate is deter-
mined by the selected OSR such that tCONV (ms) = (40
OSR + 170)/fOSC (kHz). The first digital filter null is located
at 8/tCONV, 7kHz at OSR = 256 and 55Hz (Simultaneous 50/
60Hz) at OSR = 32768. This pin may be driven with a
maximum external clock of 10.24MHz resulting in a maxi-
mum 8kHz output rate (OSR = 64, 2x Mode).
CS (Pin 36): Active Low Chip Select. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this low power state as long
as CS is HIGH. A LOW-to-HIGH transition on CS during the
Data Output aborts the data transfer and starts a new
conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the conversion and sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS
LOW. This signal is HIGH while the conversion is in
progress and goes LOW once the conversion is complete.
SCK (Pin 38): Bidirectional Digital Clock Pin. In internal
serial clock operation mode, SCK is used as a digital output
for the internal serial interface clock during the data output
period. In the external serial clock operation mode, SCK is
used as the digital input for the external serial interface
clock during the data output period. The serial clock
operation mode is determined by the logic level applied to
the EXT pin.
Exposed Pad (Pin 39): Ground. The exposed pad on the
bottom of the package must be soldered to the PCB ground.
For Prototyping purposes, this pin may remain floating.
– 0.3V to VCC + 0.3V. Within these limits, the two selected
inputs (IN+ and IN–) provide a bipolar input range (VIN =
IN+ – IN–) from –0.5 VREF to 0.5 VREF. Outside this input
range, the converter produces unique over-range and
under-range output codes.
CH0 to CH7 (Pins 8, 9, 12, 13, 16, 17, 20, 21): Analog
Inputs. May be programmed for Single-ended or Differen-
tial mode.
VREF01+ (Pin 11), VREF01– (Pin 10) VREF23+ (Pin 15),
VREF23– (Pin 14), VREF45+ (Pin 19), VREF45– (Pin 18),
VREF67+ (Pin 23), VREF67– (Pin 22): Differential Reference
Inputs. The voltage on these pins can be anywhere
between 0V and VCC as long as the positive reference
input (VEF01+, VREF23+, VREF45+, VREF67+) is greater than
the corresponding negative reference input (VREF01–,
VREF23–, VREF45–, VREF67–) by at least 100mV.
NC (Pins 24, 25, 26, 27): LTC2446 No Connect. These
pins can either be tied to ground or left floating.
MUXOUTP (Pin 24): LTC2447 Positive Input Channel
Multiplexer Output. Used to drive the input to an external
buffer/amplifier for the selected positive input signal (IN+).
ADCINP (Pin 25): LTC2447 Positive ADC Input. Tie to
output of buffer/amplifier driven by MUXOUTP.
ADCINN (Pin 26): LTC2447 Negative ADC Input. Tie to
output of buffer/amplifier driven by MUXOUTN.
MUXOUTN (Pin 27): LTC2447 Negative Input Channel
Multiplexer Output. Used to drive the input to an external
buffer/amplifier for the selected negative input signal
(IN–).
VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10
F tantalum capacitor in parallel with a 0.1F ceramic
capacitor as close to the part as possible.
VREFG+ (Pin 29), VREFG– (Pin 30): Global Reference Input.
This differential reference input can be used for any input
channel selected through a single bit in the digital input word.
SDI (Pin 34): Serial Data Input. This pin is used to select
the speed, 1x or 2x mode, resolution, input channel and
reference input for the next conversion cycle. At initial
power-up, the default mode of operation is CH0-CH1,
VREF01, OSR of 256, and 1x mode. The serial data input
PI FU CTIO S
UU
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