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参数资料
| 型号： | LTC2451ITS8#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 2/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT DELTA SIG TSOT23-8 |
| 标准包装： | 2,500 |
| 位数： | 16 |
| 采样率（每秒）： | 60 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.2mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 薄型，TSOT-23-8 |
| 供应商设备封装： | TSOT-23-8 |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个单端，单极 |
| 配用： | DC1383A-A-ND - BOARD DELTA SIGMA ADC LTC2451 |
LTC2451
10
2451fg
Data Transferring
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a not-acknowledge (NACK) by leaving the
SDA line high impedance (the external pull-up resistor will
hold the line high). Change of data only occurs while the
clock line (SCL) is low.
Data Format
After a START condition, the master sends a 7-bit address
(factory set at 0010100), followed by a read request (R)
or write request (W) bit. The bit R is 1 for a read request
and 0 for a write request. If the 7-bit address agrees with
the LTC2451’s address, the device is selected. When the
device is addressed during the conversion state, it does
not accept the request and issues a NACK by leaving the
SDA line high. If the conversion is complete, the LTC2451
issues an ACK by pulling the SDA line LOW.
The user can send one byte of data into the LTC2451 fol-
lowing a write request and an ACK. The sequence is shown
in Figure 3. The write sequence is used solely to set the
conversion speed. The default conversion speed is 60Hz.
The user can specify a 30Hz conversion speed by setting
the eighth bit (S30) = 1, or specify a 60Hz conversion
speed by setting the eighth bit (S30) = 0.
After a read request and an ACK, the LTC2451 can output
data, as shown in Figure 4. The data output stream is 16
bits long and is shifted out on the falling edges of SCL.
APPLICATIONS INFORMATION
Figure 3. Timing Diagram for Write Sequence
Figure 4. Timing Diagram for Read Sequence
1
7
8
9
2
3
1
4
S30
W
SDA
SCL
7-BIT
ADDRESS
START BY
MASTER
S30 = 1: 30Hz MODE
S30 = 0: 60Hz MODE
5
6
7
8
9
ACK BY
LTC2451
SLEEP
DATA INPUT
2451 F03
ACK BY
MASTER
1
7
8
9
2
3
1
8
D8
D13
D14
MSB
D15
R
SDA
SCL
7-BIT
ADDRESS
START BY
MASTER
D7
D6
D5
D0
LSB
9
1
2
3
8
9
ACK BY
LTC2451
ACK BY
MASTER
NACK BY
MASTER
SLEEP
DATA OUTPUT
CONVERT
2451 F04
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