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参数资料
| 型号： | LTC2452ITS8#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 2/22页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT DELTA SIG TSOT23-8 |
| 标准包装： | 2,500 |
| 位数： | 16 |
| 采样率（每秒）： | 60 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 2.4mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 薄型，TSOT-23-8 |
| 供应商设备封装： | TSOT-23-8 |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | DC1384A-A-ND - BOARD DELTA SIGMA ADC LTC2452 |
LTC2452
10
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
2) After the 16th bit is read, the user can choose one of
two ways to begin a new conversion. First, one can
pull CS high (CS =
↑). Second, one can use a high-low
transition on SCK (SCK =
↓).
3) At any time during the Data Output state, pulling CS
high (CS =
↑) causes the part to leave the I/O state,
abort the output and begin a new conversion.
4) When SCK = HIGH, it is possible to monitor the conver-
sion status by pulling CS low and watching for SDO to
go low. This feature is available only in the idle-high
(CPOL = 1) mode.
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2452
automatically enters the low power sleep mode. The user
can monitor the conversion status at convenient intervals
using CS and SDO.
Pulling CS LOW while SCK is HIGH tests whether or not
the chip is in the CONVERT state. While in the CONVERT
state, SDO is HIGH while CS is LOW. In the SLEEP state,
SDO is LOW while CS is LOW. These tests are not required
operational steps but may be useful for some applications.
When the datais available, the user applies 16 clock cycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
The operation example of Figure 7 is identical to that of
Figure 6, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK). A 17th clock
pulse is used to trigger a new conversion cycle.
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 8, following a conversion cycle the LTC2452
automatically enters the low-power sleep state. The user
determines data availability (and the end of conversion)
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
Figure 7. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
D15
clk1
clk2
clk3
clk4
clk15
clk16
D14
D13
D12
D2
D1
D0
SD0
SCK
CONVERT
SLEEP
DATA OUTPUT
2452 F06
CS
D15
D14
D13
D12
D2
D1
D0
SD0
clk1
clk2
clk3
clk4
clk15
clk16
clk17
SCK
CONVERT
SLEEP
DATA OUTPUT
2452 F07
CS
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