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| 型号： | LTC2452ITS8#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/22页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT DELTA SIG TSOT23-8 |
| 标准包装： | 2,500 |
| 位数： | 16 |
| 采样率（每秒）： | 60 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 2.4mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 薄型，TSOT-23-8 |
| 供应商设备封装： | TSOT-23-8 |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | DC1384A-A-ND - BOARD DELTA SIGMA ADC LTC2452 |
LTC2452
14
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
PRESERVING THE CONVERTER ACCURACY
The LTC2452 is designed to minimize the conversion
result’s sensitivity to device decoupling, PCB layout,
anti-aliasing circuits, line and frequency perturbations.
Nevertheless, in order to preserve the high accuracy capa-
bility of this part, some simple precautions are desirable.
Digital Signal Levels
DuetothenatureofCMOSlogic,itisadvisabletokeepinput
digital signals near GND or VCC. Voltages in the range of
0.5V to VCC – 0.5V may result in additional current leakage
from the part. Undershoot and overshoot should also be
minimized, particularly while the chip is converting. It is
thus beneficial to keep edge rates of about 10ns and limit
overshoot and undershoot to less than 0.3V.
Noisy external circuitry can potentially impact the output
under 2-wire operation. In particular, it is possible to get
the LTC2452 into an unknown state if an SCK pulse is
missed or noise triggers an extra SCK pulse. In this situ-
ation, it is impossible to distinguish SDO = 1 (indicating
conversion in progress) from valid “1” data bits. As such,
CPOL = 1 is recommended for the 2-wire mode. The user
should look for SDO = 0 before reading data, and look
for SDO = 1 after reading data. If SDO does not return a
“0” within the maximum conversion time (or return a “1”
after a full data read), generate 16 SCK pulses to force a
new conversion.
Driving VCC and GND
In relation to the VCC and GND pins, the LTC2452 com-
bines internal high frequency decoupling with damping
elements, which reduce the ADC performance sensitivity
to PCB layout and external components. Nevertheless, the
very high accuracy of this converter is best preserved by
careful low and high frequency power supply decoupling.
A 0.1F, high quality, ceramic capacitor in parallel with
a 10F ceramic capacitor should be connected between
the VCC and GND pins, as close as possible to the pack-
age. The 0.1F capacitor should be placed closest to the
ADC package. It is also desirable to avoid any via in the
circuit path, starting from the converter VCC pin, passing
through these two decoupling capacitors, and return-
ing to the converter GND pin. The area encompassed
by this circuit path, as well as the path length, should
be minimized.
Furthermore, as shown in Figure 15, GND is used as the
negative reference voltage. It is thus important to keep the
GNDlinequietandconnectGNDthroughalow-impedance
trace.
Very low impedance ground and power planes, and star
connections at both VCC and GND pins, are preferable. The
VCC pin should have two distinct connections: the first to
thedecouplingcapacitorsdescribedabove,andthesecond
to the ground return for the power supply voltage source.
Driving REF
A simplified equivalent circuit for REF is shown in Figure
15. Like all other A/D converters, the LTC2452 is only
as accurate as the reference it is using. Therefore, it is
important to keep the reference line quiet by careful low
and high frequency decoupling.
The LT6660 reference is an ideal match for driving the
LTC2452’s REF pin. The LTC6660 is available in a 2mm
× 2mm DFN package with 2.5V, 3V, 3.3V and 5V options.
Figure 15. LTC2452 Analog Input/Reference Equivalent Circuit
RSW
15k
(TYP)
ILEAK
VCC
CEQ
0.35pF
(TYP)
IN+
IN–
GND
REF
2452 F15
RSW
15k
(TYP)
ILEAK
RSW
15k
(TYP)
ILEAK
RSW
15k
(TYP)
ILEAK
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