参数资料
| 型号： | LTC2485CDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 3/40页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT I2C 10-DFN |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 6.8 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 480µW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 供应商设备封装： | 10-DFN（3x3） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，双极 |
| 配用： | DC956A-ND - BOARD DELTA SIGMA ADC LTC2485 |
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LTC2485
11
2485fc
PIN FUNCTIONS
REF+ (Pin 1), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF+, is
more positive than the reference negative input, REF –,
by at least 0.1V.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1μF tantalum capacitor in parallel with 0.1μF
ceramic capacitor as close to the part as possible.
IN+ (Pin 4), IN– (Pin 5):
Differential Analog Input. The volt-
age on these pins can have any value between GND – 0.3V
and VCC + 0.3V. Within these limits the converter bipolar
input range (VIN = IN+ – IN–) extends from –0.5 VREF to
0.5 VREF. Outside this input range the converter produces
unique overrange and underrange output codes.
SCL (Pin 6): Serial Clock Pin of the I2C Interface. The
LTC2485 can only act as a slave and the SCL pin only
accepts external serial clock. Data is shifted into the
SDA pin on the rising edges of the SCL clock and out-
put through the SDA pin on the falling edges of the
SCL clock.
SDA (Pin 7): Bidirectional Serial Data Line of the I2C Inter-
face. In the transmitter mode (Read), the conversion result
is output through the SDA pin, while in the receiver mode
(Write), the device conguration bits are input through the
SDA pin. At data input mode, the pin is high impedance;
while at data output mode, it is an open-drain N-channel
driver and therefore an external pull-up resistor or current
source to VCC is needed.
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is
congured as a three state (LOW, HIGH, or Floating) ad-
dress control bit for the device I2C address.
CA0/f0 (Pin 10): Chip Address Control Pin/External Clock
Input Pin. When no transition is detected on the CA0/f0
pin, it is a two state (HIGH or Floating) address control
bit for the device I2C address. When the pin is driven by
an external clock signal with a frequency fEOSC of at least
10kHz, the converter uses this signal as its system clock
and the fundamental digital lter rejection null is located
at a frequency fEOSC/5120 and sets the Chip Address CA0
internally to a HIGH.
FUNCTIONAL BLOCK DIAGRAM
6
7
4
5
9
10
3RD ORDER
ADC
REF+
IN+
1
REF+
IN–
REF–
I2C
SERIAL
INTERFACE
TEMP
SENSOR
MUX
SCL
2
VCC
3
REF–
8
GND
CA0/f0
2485 FB
SDA
CA1
AUTOCALIBRATION
AND CONTROL
INTERNAL
OSCILLATOR
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