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参数资料
| 型号： | LTC2492IDE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT DELTA SIG 14-DFN |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 800µW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-WFDFN 裸露焊盘 |
| 供应商设备封装： | 14-DFN-EP（4x3） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，双极；2 个差分，双极 |
| 配用： | DC1009A-A-ND - BOARD DELTA SIGMA ADC LTC2492 |
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LTC2492
24
2492fd
APPLICATIONS INFORMATION
After the 32nd rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH any time between the 1st rising edge and
the 32nd falling edge of SCK (see Figure 10). On the ris-
ing edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter conguration remains
unchanged. In order to program both the input channel
and converter conguration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 11). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is oating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has nished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
Figure 9. Internal Serial Clock, Single Cycle Operation
Hi-Z
2492 F09
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
VCC
fO
SCK
SDI
GND
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2492
4-WIRE
SPI INTERFACE
EOC
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
BIT 20 BIT 19
BIT 29
BIT 30
BIT 31
BIT 18 BIT 17
BIT 0
12
3
4
5
6
7
8
9
10
11
12
13
14
32
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
DON'T CARE
MSB
SIG
“0”
OPTIONAL
10k
VCC
<tEOCTEST
REF+
REF–
CH0
CH1
CH2
CH3
COM
CS
12
1
13
14
8
9
10
11
7
3
4
6
5
2
2.7V TO 5.5V
0.1μF
10μF
SDO
CONVERSION
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