- 您现在的位置：买卖IC网 > PDF目录8661 > LTC2607IDE-1#TRPBF (Linear Technology)IC DAC 16BIT R-R I2C 12-DFN PDF资料下载
参数资料
| 型号： | LTC2607IDE-1#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 5/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT R-R I2C 12-DFN |
| 标准包装： | 2,500 |
| 设置时间： | 10µs |
| 位数： | 16 |
| 数据接口： | I²C |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 780µW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-WFDFN 裸露焊盘 |
| 供应商设备封装： | 12-DFN（4x3） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电压，单极 |
| 采样率（每秒）： | * |
| 配用： | DC934A-ND - BOARD DAC LTC2607 |
LTC2607/LTC2617/LTC2627
26071727fa
operation
specifications. For an I2C bus operating in the fast mode,
an active pull-up will be necessary if the bus capacitance is
greater than 200pF. The VCCpowershouldnotberemoved
from the LTC2607/LTC2617/LTC2627 when the I2C bus
is active to avoid loading the I2C bus lines through the
internal ESD protection diodes.
The LTC2607/LTC2617/LTC2627 are receive-only (slave)
devices. The master can write to the LTC2607/LTC2617/
LTC2627.TheLTC2607/LTC2617/LTC2627donotrespond
to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the lat-
est byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releasestheSDAline(HIGH)duringtheAcknowledgeclock
pulse. The slave-receiver must pull down the SDA bus line
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse.
The LTC2607/LTC2617/LTC2627 respond to a write by a
master in this manner. The LTC2607/LTC2617/LTC2627
do not acknowledge a read (retains SDA HIGH during the
period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: VCC, GND or float. This results
Power-On Reset
The LTC2607/LTC2617/LTC2627 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2607-1/
LTC2617-1/LTC2627-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2607/
LTC2617/LTC2627 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 9) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limitsduringpowersupplyturn-onandturn-offsequences,
when the voltage at VCC (Pin 8) is in transition.
Transfer Function
The digital-to-analog transfer function is:
V
k
V
OUT IDEAL
N
REF
REFLO
(
) =
(
)+
2
where k is the decimal equivalent of the binary DAC
input code, N is the resolution and VREF is the voltage at
REF (Pin 6).
Serial Digital Interface
The LTC2607/LTC2617/LTC2627 communicate with a
host using the standard 2-wire I2C interface. The Timing
Diagrams (Figures 1 and 2) show the timing relationship
of the signals on the bus. The two bus lines, SDA and
SCL, must be high when the bus is not in use. External
pull-up resistors or current sources are required on these
lines. The value of these pull-up resistors is dependent
on the power supply and can be obtained from the I2C
相关PDF资料 |
PDF描述 |
|---|---|
| VE-J23-MY | CONVERTER MOD DC/DC 24V 50W |
| VE-J22-MY | CONVERTER MOD DC/DC 15V 50W |
| AD8802ARZ | IC DAC 8BIT 12CH W/SD 20SOIC |
| VI-JWZ-MW | CONVERTER MOD DC/DC 2V 40W |
| VI-JWY-MY | CONVERTER MOD DC/DC 3.3V 33W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2609CGN#PBF | 功能描述:IC DAC 16BIT R-R QUAD 16SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| LTC2609CGN#TRPBF | 功能描述:IC DAC 16BIT R-R QUAD 16SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| LTC2609CGN-1#PBF | 功能描述:IC DAC 16BIT R-R QUAD 16SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| LTC2609CGN-1#TRPBF | 功能描述:IC DAC 16BIT R-R QUAD 16SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:2,400 系列:- 设置时间:- 位数:18 数据接口:串行 转换器数目:3 电压电源:模拟和数字 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:36-TFBGA 供应商设备封装:36-TFBGA 包装:带卷 (TR) 输出数目和类型:* 采样率（每秒）:* |
| LTC2609IGN#PBF | 功能描述:IC DAC 16BIT R-R QUAD 16SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
发布紧急采购，3分钟左右您将得到回复。