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参数资料
| 型号： | LTC2902-1IGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC MON SUPP QD W/RST&SEL 16-SSOP |
| 标准包装： | 100 |
| 类型： | 多压监控器 |
| 监视电压数目： | 4 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 最小为 5 ms |
| 电压 - 阀值： | 16 种可选阀值组合 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 管件 |
LTC2902
APPLICATIO S I FOR ATIO
Power-Up
On power-up, the larger of V1 or V2 will power the drive
circuits for the RST and the COMPX pins. This ensures
LTC2902
V REF
V PG
GND
12
11
10
R1
1%
R2
1%
that the RST and COMPX outputs will be low as soon as
V1 or V2 reaches 1V. The RST and COMPX outputs will
remain low until the part is programmed. After program-
2902 F04
Figure 4. Monitor Programming
ming, if any one of the V X inputs is below its programmed
threshold, RST will be a logic low. Once all the V X inputs
rise above their thresholds, an internal timer is started
and RST is released after the programmed delay time. If
Table 1. Voltage Threshold Programming
MODE V1 (V) V2 (V) V3 (V) V4 (V) R1 (k ? ) R2 (k ? )
0 5.0 3.3 ADJ ADJ Open Short
V PG
V REF
0.000
V CC < (V3 – 1) and V CC < 2.4V, the V3 input impedance
will be low (1k ? typ).
Monitor Programming
The LTC2902 input voltage combination is selected by
placing the recommended resistor divider from V REF to
GND and connecting the tap point to V PG , as shown in
Figure 4. Table 1 offers recommended 1% resistor values
for the various modes. The last column in Table 1 speci-
fies optimum V PG /V REF ratios ( ± 0.01) to be used when
programming with a ratiometric DAC.
During power-up, once V1 or V2 reaches 2.4V (max), the
monitor enters a programming period of approximately
150 μ s during which the voltage on the V PG pin is sampled
and the monitor is configured to the desired input combi-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5.0
3.3
3.3
3.3
5.0
5.0
5.0
5.0
5.0
3.3
3.3
3.3
5.0
5.0
5.0
3.3
2.5
2.5
2.5
3.3
3.3
3.3
3.0
3.0
2.5
2.5
2.5
3.3
3.3
3.0
ADJ
ADJ
ADJ
1.5
2.5
2.5
2.5
2.5
ADJ
1.8
1.8
1.8
1.8
1.8
1.8
–ADJ
ADJ
–ADJ
ADJ
ADJ
1.8
1.5
ADJ
ADJ
1.5
ADJ
–ADJ
–ADJ
ADJ
ADJ
93.1
86.6
78.7
71.5
66.5
59.0
53.6
47.5
40.2
34.8
28.0
22.1
16.2
9.53
Short
9.53
16.2
22.1
28.0
34.8
40.2
47.5
53.6
59.0
66.5
71.5
78.7
86.6
93.1
Open
0.094
0.156
0.219
0.281
0.344
0.406
0.469
0.531
0.594
0.656
0.719
0.781
0.844
0.906
1.000
nation. Do not add capacitance to the V PG pin. Immediately
after programming, the comparators are enabled and
supply monitoring will begin.
Supply Monitoring
The LTC2902 is a low power, high accuracy program-
mable quad supply monitoring circuit with four nondelayed
monitor outputs, a common reset output and selectable
supply thresholds. Reset timing is adjustable using an
The inverting inputs on the V3 and/or V4 comparators are
set to 0.5V when the positive adjustable modes are selected
and with T0 and T1 low (5% tolerance) (Figure 5). The tap
point on an external resistive divider, connected between
the positive voltage being sensed and ground, is connected
to the high impedance noninverting inputs (V3, V4). The
trip voltage is calculated from:
V TRIP = 0 . 5 V ? 1 +
?
externalcapacitor.Singlepinprogrammingselects1of16
input voltage monitor combinations. Two digital inputs
select one of four supply tolerances (5%, 7.5%, 10% or
?
?
R 3 ?
R 4 ?
12.5%). All four voltage inputs must be above predeter-
mined thresholds for the reset not to be invoked. The
LTC2902 will assert the reset and comparator outputs
during power-up, power-down and brownout conditions
on any one of the voltage inputs.
Once the resistor divider is set in the 5% tolerance mode,
there is no need to change the divider for the other
tolerance modes (7.5%, 10%, 12.5%) because the inter-
nal reference is scaled accordingly, moving the trip point
in – 2.5% increments.
2902f
10
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