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参数资料
| 型号： | LTC2919HDDB-2.5#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10 |
| 封装： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10 |
| 文件页数： | 4/16页 |
| 文件大小： | 195K |
| 代理商： | LTC2919HDDB-2.5#PBF |
LTC2919
12
2919f
To minimize errors arising from ADJ input bias and to
minimize loading on REF choose resistor RP1 (for positive
supply monitoring) or RN1(fornegativesupplymonitoring)
in the range of 5k to 100k.
For a positive-monitoring application, RP2 is then chosen
by:
RP2 = RP1(2VTRIP – 1)
For a negative-monitoring application:
RN2 = RN1(1 – 2VTRIP)
Note that the value VTRIP should be negative for a negative
application.
The LTC2919 can also be used to monitor a single supply
for both UV and OV. This may be accomplished with three
resistors, instead of the four required for two independent
supplies. Congurations are shown in Figures 3 and 4. RP4
or RN4 may be chosen as is RP1 or RN1 above.
For a given RP4, monitoring a positive supply:
R
P5 = RP4
V
OV –VUV
V
UV
R
P6 = RP4 2VUV –1
()
V
OV
V
UV
For monitoring a negative supply with a given RN4:
R
N5 = RN4
V
UV –VOV
1– V
UV
R
N6 = RN4 1– 2VUV
()
1– V
OV
1– V
UV
Forexample,considermonitoringa–5Vsupplyat±10%.For
this supply application: VOV = –5.575V and VUV = –4.425V.
Suppose we wish to consume about 5μA in the
divider, so
RN4=100k.WethenndRN5=21.0k,RN6=1.18M(nearest
1% standard values have been chosen).
VCC Monitoring/UVLO
The LTC2919 contains an accurate third -10% undervoltage
monitor on the VCC pin. This monitor is xed at a nominal
11.5% below the VCC specied in the part number. The
standard part (LTC2919-2.5) is congured to monitor a
2.5V supply (UVLO threshold of 2.213V), but versions
to monitor 3.3V and 5.0V (UVLO of 2.921V and 4.425V,
respectively) are available.
For applications that do not need VCC monitoring, the
2.5V version should be used, and the UVLO will simply
guarantee that the VCC is above the minimum required for
proper threshold and timer accuracy before the timeout
begins.
Setting the Reset Timeout
RST goes high after a reset timeout period set by the TMR
pin when the VCC and ADJ inputs are valid. This reset
timeout may be congured in one of three ways: internal
200ms, programmed by external capacitor and no timeout
(comparator mode).
In externally-controlled mode, the TMR pin is connected
by a capacitor to ground. The value of that capacitor allows
for selection of a timeout ranging from about 400μs to 9
seconds. See the following section for details.
APPLICATIO S I FOR ATIO
WU
U
–
+
–
+
–
0.5V
2919 F03
ADJ1
OUT1
OUT2
UV
OV
ADJ2
VMON
RP5
RP6
RP4
LOGIC
&
OPEN
DRAIN
MOSFET
LOGIC
&
OPEN
DRAIN
MOSFET
Figure 3. Setting UV and OV Trip Point for a Positive Supply
–
+
–
+
–
0.5V
2919 F04
ADJ2
ADJ1
REF
–VMON
RN5
RN4
RN6
OUT1
OUT2
OV
UV
LOGIC
&
OPEN
DRAIN
MOSFET
LOGIC
&
OPEN
DRAIN
MOSFET
Figure 4. Setting UV and OV Trip Point for a Negative Supply
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